Timeline for Irregularly triggering an ISR using timers
Current License: CC BY-SA 3.0
7 events
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| Mar 31, 2016 at 12:11 | comment | added | mike | Thanks for the additional explanation. I was originally worried about the flag, that was set on compare match, but now I totally agree, that stopping the timer is what I was looking for! | |
| Mar 31, 2016 at 12:10 | vote | accept | mike | ||
| Mar 29, 2016 at 20:45 | comment | added | Nick Gammon♦ | See amended answer. | |
| Mar 29, 2016 at 20:45 | history | edited | Nick Gammon♦ | CC BY-SA 3.0 |
Added more explanations.
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| Mar 29, 2016 at 7:54 | comment | added | mike | btw.: looking at your divisioning of the time axis, and from code, it is clear, that there is a 600us break, not 1ms! Since both timers (timer0 running micros() and timer2) run parallel, it is clear, that the break is 1ms-400us = 600us. | |
| Mar 29, 2016 at 6:48 | comment | added | mike |
As far as I can tell, the only additional thing is TIFR2 = bit (OCF2A);. In your code, you stop the timer alltogether. Isn't it cleaner the way I did, where I just disconnect the timer from the interrupt? In my example I do not have to set so many settings each time I want to start the timer. Or is it even desirable to use the overflow timer instead,... would that result in less hastle when starting the timer?
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| Mar 29, 2016 at 0:41 | history | answered | Nick Gammon♦ | CC BY-SA 3.0 |