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  • My reading of the datasheet (see section 7.8) makes me think the flags are cleared at ISR entry. Only the GIE is enabled during RETI (it specifically mentions it) and it reads like it's at the start of the ISR that the flag is cleared: "The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag.". Commented May 23, 2016 at 13:15
  • For the RETI it says: "A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set." - So yes, it is very very woolly in its wording, but I would lean towards the interrupt flags not being available to read in the ISR, which is a bit poor really. Personally I prefer the Microchip method where it is up to the user to manually clear the interrupt flag when it is finished with. Commented May 23, 2016 at 13:16
  • Thanks for the response, I'll test this method and post whether or not I can get it to work. Commented May 23, 2016 at 14:34
  • @Majenko: The only reason I hold out any hope at all that they'd be readable within the ISR is that someone designed those registers to be readable, which would be pointless if it is cleared during ISR vectoring (not to say it wasn't done that way!). The program would only ever be able to read zero. Commented May 23, 2016 at 16:33
  • You can read them outside an ISR when the interrupt is disabled. You can use it like a flag that is set by hardware which you can then check as and when you want. You get the notification but you don't have to respond immediately. Commented May 23, 2016 at 16:34