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Jun 21, 2017 at 21:33 comment added Edgar Bonet @Jot: Yes, you could use ISR_NAKED, and that would save a few bytes of flash and RAM, and about 1.9% of CPU power. But then the ISR would clobber some CPU registers. That would be OK with the program as it is, since outside the ISR it does nothing but sleep, but it would be problematic as soon as you add code to the main loop. And no, you cannot avoid clobbering registers: it's a load/store architecture.
Jun 21, 2017 at 21:17 comment added Jot Could ISR_NAKED be used ? Perhaps asm code is needed to prevent that unknown local/register variables are used.
Jun 21, 2017 at 20:11 history edited Edgar Bonet CC BY-SA 3.0
+ link to demo program.
Jun 21, 2017 at 18:53 comment added Edgar Bonet @ChrisStratton: Yes, I tested it, it works. When the ADC finishes the (n)-th conversion, it triggers ISR(ADC_vect) and immediately starts the (n+1)-st. In the ISR, you process that (n)-th reading, and you set the MUX for the (n+2)-nd conversion. The trick is: the ADC ignores the new MUX setting until it is ready to start a new conversion. I will shortly upload a program demonstrating the approach.
Jun 21, 2017 at 18:18 comment added Chris Stratton Are you sure that you can achieve this rate with the stock software when switching channels and never be delayed in switching by a timer interrupt being in progress at the key time? If the ADC block can handle the channel switching automatically, the answer may be yes, if not, the answer is no, and those ideas you are dismissing as "useless" may actually be required.
Jun 21, 2017 at 9:23 history answered Edgar Bonet CC BY-SA 3.0