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    Even in Skylake, one dpps is 4 uops, 13c latency. (But one per 1.5c throughput). haddps is 3uops, 6c latency. (one per 2c throughput). Store and scalar is not too bad because it doesn't cost many uops, but it's pretty bad for latency compared to Kornel's answer. Scalar ops have the same latency as vector ops, though. Your "tightly pipelined using register bypass" speculation isn't correct. Everything except div is fully pipelined, but you're right that horizontal instructions aren't fast-pathed. They're decoded to internal shuffle uops. Commented Feb 7, 2016 at 17:20