Francisco Esteves

Cerebras Systems inside of Cline provides lightning fast inference inside your developer workflow. Here is a quick tutorial showing just how easy it is. There are lots of things worth waiting for. Inference results aren't among them. Build with the fastest...

١٧٧

Just one month after announcing our partnership with OpenAI, we’re launching our first model together: OpenAI Codex-Spark, powered by Cerebras. Codex-Spark is built for real-time software development. In coding, responsiveness is the product. It is not a nice to have. Codex-Spark is optimized for targeted code edits, logic revisions, and frontend iteration. It gives developers near-instant feedback so they can stay in flow. Powered by the Cerebras Wafer-Scale Engine, it runs at over 1,000 tokens/s. That speed fundamentally changes the experience. We did not build this to win a benchmark. We built it so developers could move faster. I’m proud of how quickly the OpenAI and Cerebras teams have brought this to life. This is what fast execution looks like - deep engineering collaboration, rapid iteration, and shipping real products developers can use today. We are just getting started. When inference is fast, entirely new markets open up. We plan to lead that shift with our partners at OpenAI.

١٬٢٤٦

٥٢ تعليق

Yesterday, I shared the big step forward with Cerebras Systems integration into Meta’s flagship new Llama API. What’s in it for developers? 1/ The fastest Llama 4 inference in the world. —18x faster than GPUs, 4x faster than the next best 2/ Full accuracy — native 8/16-bit, no compromises 3/Easy migration — 1-click API and 3 code changes to switch from OpenAI 4/ No lock-in — prompts and outputs remain yours, with full provider portability 5/ Production-ready — consistent, predictable speeds at scale Can’t wait to see the innovations that the AI community will unlock 🔓 ⚙️ 👊

٢٧٧

٥ تعليق

Leading AI token providers like OpenRouter and Hugging Face publish the daily performance of their API partners. This provides their customers and the community in general full transparency with regard to performance and latency. Today's OpenRouter dashboard shows that Cerebras Systems 10 times faster, at 1/6th the latency, of the next nearest competitor on DeepSeek's R1 70B model. Cerebras Systems is 40 times faster than the fastest GPU based solution provider.

٩٧

٢ تعليق

🚀 Exploring Zephyr RTOS: From Source to Execution on QEMU When we talk about modern embedded development, one project that consistently stands out is Zephyr RTOS. 🔹 What is Zephyr? Zephyr is a scalable, real-time operating system (RTOS) built for resource-constrained devices, supporting architectures ranging from tiny microcontrollers to full x86 systems. Backed by the Linux Foundation and adopted by industry leaders, Zephyr provides: Deterministic real-time scheduling Rich driver support (sensors, networking, storage, BLE, etc.) Security and modularity at its core A truly community-driven ecosystem In short, Zephyr bridges the gap between bare-metal firmware and full-scale Linux systems, making it a powerful choice for IoT and embedded innovation. 🔹 Running Zephyr on QEMU (x86) One of Zephyr’s strengths is its QEMU support, which allows developers to test applications even without physical hardware. This accelerates learning, prototyping, and debugging. Here’s a glimpse from my recent run: *** Booting Zephyr OS build v4.2.0 *** Hello World! qemu_x86/atom Seeing that “Hello World!” from a minimal RTOS, built with west build and running inside QEMU, is a reminder of how far embedded development has evolved. With just a few commands, we can spin up a virtual environment emulating an x86 target — no board required. 🔹 Why this matters Teams can prototype firmware quickly without waiting for hardware. CI/CD pipelines can integrate QEMU to run automated RTOS tests. Students and enthusiasts can learn RTOS fundamentals on any laptop. The combination of Zephyr + QEMU makes embedded development more accessible, scalable, and future-proof. 🌍 Whether you're an IoT enthusiast, a professional building safety-critical systems, or a student stepping into the world of embedded systems — Zephyr is worth exploring. 💡 Next step: I’ll be diving deeper into drivers, scheduling, and eventually deploying Zephyr builds on real ARM-based boards. #ZephyrRTOS #EmbeddedSystems #QEMU #IoT #RTOS #TechDhaba

٥٤

٣ تعليق

The RISC-V vs ARM debate has become nothing more than tech tribalism that makes engineers feel virtuous while completely overlooking what actually determines project success in the real world. We've all encountered, 'RISC-V will democratize computing with its open-source model!' But let's be brutally honest: in 80% of commercial deployments, ecosystem availability beats architectural ideals every time. The countless hours spent battling incompatible RISC-V toolchains could have been invested in optimizing ARM-based solutions. And don't get me started on teams that select RISC-V for 'openness' only to find their custom ISA extensions have locked them into a single vendor more tightly than ARM's licensing ever could. I've observed directly projects hemorrhage 6 months just to get basic RISC-V compiler support working reliably for standard peripherals, while comparable ARM implementations reached production in 8 weeks leveraging battle-tested CMSIS drivers. The most ironic part? The 'open-source' narrative conveniently obscures that 70% of production RISC-V systems rely on proprietary extensions and commercial toolchains - you're essentially swapping ARM's licensing costs for RISC-V vendor support agreements. What we genuinely need is ruthless pragmatism: ARM when time-to-market and peripheral support are critical, RISC-V when custom accelerators or extreme cost constraints drive the design. This isn't compromise - it's engineering common sense. When your product launch is next quarter and you need functional WiFi, BLE, and security subsystems, every absent driver in the RISC-V ecosystem directly threatens your schedule. The next time you feel drawn to RISC-V for ideological reasons, ask yourself: Will this choice genuinely accelerate my development timeline, or am I volunteering to be a toolchain guinea pig? ⚖️ What single factor tipped the scales between RISC-V and ARM in your last project? Share your make-or-break decision criteria below - bonus points for how you'd evaluate the trade-off differently today! #RISCV #ARM #EmbeddedSystems #ProcessorArchitecture #EngineeringReality #EcosystemMaturity #TechChoices #DeveloperExperience #FPGA #SoC #CostOptimization #TimeToMarket

١٦٧

١٧ تعليق

Bringing Linux developers into Zephyr? Easy. Bringing embedded developers into Zephyr? That’s a different story. Some say Zephyr is “easy.” Others say it’s “hard.” The truth? It depends on where you’re coming from. Zephyr comes from the Linux Foundation, so naturally, it borrows a lot from Linux. For Linux developers, that’s a good thing. Familiar tooling, familiar concepts. They dive in and feel right at home. But for embedded developers? It’s a culture shock. Device trees, Kconfig, west… things they’ve never had to think about before. That’s why they say Zephyr has a steep learning curve. The reality? Zephyr isn’t inherently easy or hard. It’s just a matter of perspective. What do you think? How has your experience with Zephyr been so far? Let me know in the comments below 👇

٣٦١

٧٧ تعليق

In my latest #Zephyr video, I demonstrate how to connect OpenOCD to GDB and perform step-through debugging. It takes a little bit of configuring, but the toolchain is worth it for #embedded #programming. 👇👇👇 https://lnkd.in/e28zNd2z #IoT #microcontroller #ESP32 The Zephyr Project

٢١٢

٤ تعليق

🤩 This is a really cool open-source agentic RAG solution that’s super low effort to get started (32k stars ⭐ ), supports many types of data sources, and is MCP compatible too! If your data is spread across multiple platforms and you want a ChatGPT-like interface to talk to it, reason, and plan, the only real option right now is Claude Desktop—which only supports a few approved MCP servers. This one’s a much more flexible open-source alternative with tons of integrations. You can just use natural language and get going. They claim to support enterprise-scale data. I haven’t tested that, but I connected it to my Notion, Slack, and Stripe and it works well for personal use. For how little effort it takes to set up, it’s very impressive! Link: https://lnkd.in/e9FrgZnt

٣٥٠

٩ تعليق

🔒 What Really Happens If an Interrupt Occurs While Holding a Spinlock? When developing Linux kernel drivers, we often use spinlocks to protect shared resources in atomic contexts. But what if an interrupt fires while you’re already holding a spin_lock()? Let’s understand this and how to choose the right API 👇 ⚙️ The Problem with spin_lock(&lock) spin_lock() disables preemption, but interrupts are still enabled. So if an interrupt occurs while your code holds this lock and that ISR tries to acquire the same spinlock the CPU will spin forever, because the lock is already held. 💥 Result: a hard deadlock (CPU stuck spinning, system freeze). 🚫 Attempting to Fix It with spin_lock_irq(&lock) You might think “I’ll disable interrupts completely!” and yes, spin_lock_irq(&lock) does exactly that: it disables both preemption and interrupts on the current CPU. But here’s the catch ⚠️ If your code runs inside a section where interrupts were already disabled (by someone else earlier), calling spin_lock_irq(&lock) again will blindly disable interrupts once more and when you call spin_unlock_irq(&lock), it will unconditionally re-enable interrupts, even if they were meant to stay disabled! This can cause dangerous interrupt state mismatches and lead to unpredictable behavior. ✅ The Safe and Correct Way spin_lock_irqsave(&lock, flags) To handle this properly, use: spin_lock_irqsave(&lock, flags); /* critical section */ spin_unlock_irqrestore(&lock, flags); Here’s what it does: *Disables interrupts on the current CPU. *Saves the previous interrupt state in flags. *Restores that exact state later (using irqrestore()). So no matter where you call it inside nested sections or complex paths — the interrupt state is always restored correctly. 💡 This is the most reliable and widely used pattern in kernel driver code. 🧠 In Short *Use spin_lock() only when your shared data is never touched by interrupts. *Avoid spin_lock_irq() unless you’re 100% sure of interrupt state consistency. *Prefer spin_lock_irqsave() it’s safe, nestable, and restores the correct interrupt state every time. #Linux #BSP #DeviceDrivers #Spinlock #Interrupts #Synchronization #Embedded #Kernel

٨٠

“Anthropic recently published a blog post about building a C compiler entirely with Claude . They called it CCC (Claude’s C Compiler) and claimed it could compile the Linux kernel. 100% of the code was written by Claude Opus 4.6, a human only guided the process by writing test cases. That sounded interesting enough to test the claim and benchmark CCC against the industry standard GCC” https://lnkd.in/gUpDEU69

١٢

٣ تعليق

Zephyr is funded to sell microcontrollers and SoCs Yocto is funded to ship Linux products for 10-20 years Neither is a hobby project Neither is charity Funding them is cheaper than fragmentation Open source is not altruism. It's shared industrial infrastructure.

٤٠٠

١٤ تعليق

What to make of Qualcomm acquiring Edge Impulse? 💭 Short take: Edge AI is a "must" for the development of IoT. It makes for smarter edge processing in constrained devices (plus more data privacy). Chipmakers embed AI for faster, efficient deployment. This acquisition is the evidence of things of the market going in this direction and is a great sign for whole IoT community. —— Long take: In the past few years, we’ve witnessed a significant shift in how intelligence is embedded into connected devices. The industry has moved from basic connectivity toward on-device AI and edge computing, optimizing how data is processed and utilized. A notable transformation is happening within the foundation of edge AI solutions, which recently rebranded from TinyML to #EdgeAI Foundation at the end of last year. The motivation is clear—enhancing intelligence in resource-constrained devices to optimize data processing at the edge instead of relying solely on cloud infrastructure. Much like how LoRaWAN is limited by its data throughput, edge AI processing becomes essential for extracting value directly on the device. 𝙉𝙚𝙬 𝙢𝙤𝙙𝙚𝙡𝙨, 𝙣𝙚𝙬 𝙖𝙥𝙥𝙡𝙞𝙘𝙖𝙩𝙞𝙤𝙣𝙨 The industry is shifting towards hardware that natively supports AI models. Over the past couple of years, we’ve seen companies capitalize on this trend. For instance, a Swedish company, Imagimob, was recently acquired for an undisclosed amount by Infineon Technologies to strengthen its embedded AI and #TinyML capabilities for edge devices. Imagimob’s platform enables efficient Edge AI development, supporting applications like audio event detection, voice control, and predictive maintenance. This acquisition enhances Infineon’s product offerings, accelerating TinyML adoption and intelligent on-device processing, aligning with the industry shift toward AI-powered edge computing. The key driver? Customer base and the need for AI toolchains that accelerate chip adoption and application development. This trend is not just a passing wave; it’s the next step in embedded AI evolution. Many leading semiconductor firms are embracing this movement, integrating on-device AI capabilities into their chips to enable faster, more efficient deployments. At senzemo, we actively leverage these technologies to enhance our Custom IoT solutions. Seeing this shift unfold confirms that AI-powered edge computing is not just a possibility—it’s the future. 🌐 Are you already integrating AI at the edge? #edgeai #qualcomm #iot #lorawan #edgeimpulse

١٤١

١ تعليق واحد

𝗔𝗠𝗗 𝗶𝘀 𝗰𝗵𝗮𝗻𝗴𝗶𝗻𝗴 𝘁𝗵𝗲 𝘀𝗽𝗲𝗲𝗱 𝗼𝗳 𝗽𝗿𝗼𝗴𝗿𝗲𝘀𝘀—𝗮𝗻𝗱 𝗲𝘃𝗲𝗿𝘆𝗼𝗻𝗲 𝘀𝗲𝗲𝘀 𝗶𝘁. Alexey Navolokin has been dropping signal after signal this week about where high performance computing and AI are really headed. His updates are a reminder that we are witnessing a shift in architecture, not a trend. When you see processors hitting virtualization densities that jump by a third, when operating costs drop by nearly half in real deployments, when the independent benchmarks line up with the internal data, you know the landscape is tilting. These aren’t incremental improvements. They are architectural inflection points. One post from yesterday cuts to the heart of it. AI isn’t a gamble. It is the backbone of global productivity for the next decade. Economic models are projecting trillions in new value because compute has become the new gravity. And in that world, efficiency is everything. The new generations of hardware delivering exascale performance at lower energy draw are not just engineering wins. They are catalysts for scientific, medical, and environmental breakthroughs that only exist when raw power meets intelligent design. His commentary on collaboration this week amplifies this momentum. Performance per watt keeps rising. Efficiency scores keep breaking into new territory. Accelerator architectures are pushing faster inference speeds on large models that once required exotic hardware. Even the connective tissue—the interconnects, the adaptive fabrics, the neuromorphic principles—is evolving toward something that behaves less like a cluster and more like a living system. This is exactly why it matters to my work. When compute accelerates, autonomy accelerates. When power consumption drops, scale becomes real. When training cycles compress, intelligence becomes adaptive. The systems I build thrive when the hardware behind them stops acting like a limiter and starts acting like an engine. And right now, the engine is roaring. The ripple effects are everywhere. Drug discovery moving twice as fast. Climate science operating with clarity only supercomputers could unlock. Energy operators finding sustainable paths in a world where compute demand keeps climbing. These transformations aren’t abstract forecasts. They’re happening because the tools finally exist to make them possible. The momentum is unmistakable. The architecture is evolving. And the world is stepping into a new era of capability. Singularity Systems is looking forward to working with Alexey Navolokin and AMD

١٠٦

٣٥ تعليق

Software engineers have GitHub Copilot. Hardware engineers? I'm still waiting. ⏳ I use AI every day as a freelance hardware designer — but mostly the same way a marketing manager does. Brainstorming, proposals, architecture reviews. The moment I open my ECAD tools, the AI gets left behind. I’m copying datasheet specs into a prompt window because my design software is blind to the intelligence in my browser tab. Flux, Quilter and others are proving that generative schematics and routing can work. But most client work still lives in traditional ecosystems — and there’s a huge gap no one has bridged yet. What I want isn’t a chatbot sidebar or a faster autorouter. I want a Hardware Copilot that: ✔️ Reads datasheets and warns me when a pin is over current ✔️ Catches mismatched voltage ratings before I burn time (or boards) ✔️ Suggests routing improvements with fewer vias and cleaner paths ✔️ Knows my context, my design intent, my constraints AI shouldn’t just watch my work — it should work with me. 💪🏻 🙋‍If you could add one AI superpower to your ECAD tool, what would it be? Smart placement? Routing? Automated design review? #AI #GenerativeAI #HardwareCopilot #FutureOfEDA #PCBdesign #Altium

٢٧٤

٨٧ تعليق

𝗠𝗶𝘅𝘁𝘂𝗿𝗲 𝗼𝗳 𝗘𝘅𝗽𝗲𝗿𝘁𝘀 (𝗠𝗼𝗘): 𝗦𝗰𝗮𝗹𝗶𝗻𝗴 𝗟𝗟𝗠𝘀 𝗘𝗳𝗳𝗶𝗰𝗶𝗲𝗻𝘁𝗹𝘆 𝘄𝗶𝘁𝗵 𝗦𝗽𝗮𝗿𝘀𝗲 𝗖𝗼𝗺𝗽𝘂𝘁𝗮𝘁𝗶𝗼𝗻 Large Language Models (LLMs) continue to grow in size, pushing the limits of AI capabilities but also introducing challenges in cost, memory, and inference speed. Mixture of Experts (MoE) offers an innovative approach by using sparse computation, activating only a subset of parameters per input. Let's explore recent advances in MoE architectures and how models like DeepSeek-v2 and DeepSeek-v3 are optimizing efficiency. 🔹 𝗖𝗵𝗮𝗹𝗹𝗲𝗻𝗴𝗲𝘀 𝗶𝗻 𝗠𝗼𝗘: 𝗥𝗼𝘂𝘁𝗶𝗻𝗴 𝗕𝗼𝘁𝘁𝗹𝗲𝗻𝗲𝗰𝗸𝘀 & 𝗣𝗲𝗿𝗳𝗼𝗿𝗺𝗮𝗻𝗰𝗲 𝗧𝗿𝗮𝗱𝗲-𝗼𝗳𝗳𝘀 While MoE improves efficiency, it also faces key challenges: 𝗧𝗼𝗸𝗲𝗻 𝗗𝗿𝗼𝗽𝗽𝗶𝗻𝗴 𝗶𝗻 𝗟𝗼𝗻𝗴 𝗦𝗲𝗾𝘂𝗲𝗻𝗰𝗲𝘀: OpenMoE struggles with routing stability, sometimes losing tokens in long sequences. Fixed Routing in Pretraining: Early routing patterns can be inefficient post-training. 𝗗𝗼𝗺𝗮𝗶𝗻 𝗦𝗵𝗶𝗳𝘁 𝗜𝘀𝘀𝘂𝗲𝘀: MoE models may struggle to generalize across different data distributions. A recommended solution is incorporating instruction-following data in pretraining to enhance routing adaptability. 🚀 𝗗𝗲𝗲𝗽𝗦𝗲𝗲𝗸 𝗠𝗼𝗘: Smarter Scaling for AI Models The DeepSeek series addresses these issues with innovative optimizations: 🔸 𝗗𝗲𝗲𝗽𝗦𝗲𝗲𝗸-𝘃𝟮: 𝟮𝟯𝟲𝗕 𝗣𝗮𝗿𝗮𝗺𝗲𝘁𝗲𝗿𝘀, 𝟮𝟭𝗕 𝗔𝗰𝘁𝗶𝘃𝗲 1️⃣ Multi-Head Latent Attention (MLA): Cuts memory use by 93% with efficient KV cache storage. 2️⃣ Fine-Grained Expert Allocation: Balances shared and specialized experts across devices. 3️⃣ Device-Level Load Balancing Loss: Ensures even routing across devices, improving stability. 🔸 𝗗𝗲𝗲𝗽𝗦𝗲𝗲𝗸-𝘃𝟯: 𝗔 𝟲𝟳𝟭𝗕 𝗣𝗮𝗿𝗮𝗺𝗲𝘁𝗲𝗿 𝗠𝗼𝗱𝗲𝗹 𝘄𝗶𝘁𝗵 𝗡𝗲𝘄 𝗘𝗻𝗵𝗮𝗻𝗰𝗲𝗺𝗲𝗻𝘁𝘀 1️⃣ Multi-Token Prediction (MTP): Predicts multiple tokens at once for better efficiency. 2️⃣ Auxiliary-Loss-Free Load Balancing: Dynamically adjusts expert selection without added inefficiencies. 3️⃣ FP8 Mixed Precision Training: Reduces training costs significantly (~$5.6M for full training). 4️⃣ Extensive Post-Training: Includes context extension (128K tokens), SFT, RLHF, and knowledge distillation. 📊 𝗞𝗲𝘆 𝗧𝗮𝗸𝗲𝗮𝘄𝗮𝘆𝘀 ✅ Trained with 2.78M H800 GPU hours ✅ Performance rivals top closed-source LLMs ✅ Practical, scalable MoE for real-world deployment 🔮 𝗧𝗵𝗲 𝗙𝘂𝘁𝘂𝗿𝗲 𝗼𝗳 𝗠𝗼𝗘: 𝗘𝗳𝗳𝗶𝗰𝗶𝗲𝗻𝘁 𝗔𝗜 𝗦𝗰𝗮𝗹𝗶𝗻𝗴 MoE is revolutionizing LLM training, making sparse computation viable at scale. While early MoE models had challenges, recent breakthroughs like MLA, MTP, and smarter load balancing are proving MoE's potential. DeepSeek-v3 shows that sparse models can match dense models, signaling a shift in AI scaling strategies. What’s your take on MoE architectures? Will they define the future of AI, or do dense models still have an edge? Let’s discuss! 👇 credit : Cameron R. Wolfe, Ph.D.

١٨٥

٢٠ تعليق