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entity mux_slvv_8 is
  generic (
    PORTS  : POSITIVE  := 4
  port (
    sel  : in  STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
    X    : in  T_SLVV_8(PORTS - 1 downto 0);
    Y    : out T_SLV_8
  );
end;

entity mux_flat is
  generic (
    PORTS  : POSITIVE  := 4;
    BITS   : POSITIVE  := 8
  port (
    sel  : in  STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
    X    : in  STD_LOGIC_VECTOR((BITS * PORTS) - 1 downto 0);
    Y    : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
  );
end;

architecture rtl of mux_flat is
  type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR(BITS - 1 downto 0);
  signal mux_in : T_SLVV(PORTS - 1 downto 0)
begin
  gen : for i in 0 to PORTS - 1 generate
    -- convert flat vector to slvv
    mux_in(i) <= X(((i + 1) * BITS) - 1 downto (i * BITS));
  end generate;
  Y <= mux_in(to_integer(unsigned(sel)));
end;

entity mux_slm is
  generic (
    PORTS  : POSITIVE  := 4;
    BITS   : POSITIVE  := 8
  port (
    sel  : in  STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
    X    : in  T_SLM(PORTS - 1 downto 0, BITS - 1 downto 0);
    Y    : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
  );
end;

entity mux_slvv_8 is
  generic (
    PORTS  : POSITIVE  := 4
  );
  port (
    sel  : in  STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
    X    : in  T_SLVV_8(PORTS - 1 downto 0);
    Y    : out T_SLV_8
  );
end;

entity mux_flat is
  generic (
    PORTS  : POSITIVE  := 4;
    BITS   : POSITIVE  := 8
  );
  port (
    sel  : in  STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
    X    : in  STD_LOGIC_VECTOR((BITS * PORTS) - 1 downto 0);
    Y    : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
  );
end;

architecture rtl of mux_flat is
  type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR(BITS - 1 downto 0);
  signal mux_in : T_SLVV(PORTS - 1 downto 0)
begin
  gen : for i in 0 to PORTS - 1 generate
    -- convert flat vector to slvv
    mux_in(i) <= X(((i + 1) * BITS) - 1 downto (i * BITS));
  end generate;
  Y <= mux_in(to_integer(unsigned(sel)));
end;

entity mux_slm is
  generic (
    PORTS  : POSITIVE  := 4;
    BITS   : POSITIVE  := 8
  );
  port (
    sel  : in  STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
    X    : in  T_SLM(PORTS - 1 downto 0, BITS - 1 downto 0);
    Y    : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
  );
end;

Edit:

Here is the package PoC.common.vectors. It's included in my PicoBlaze Library which is currently in beta state. The release of PoC is also planned, but not so progressed. So I included some necessary packages and modules into this library. The source code license is 'Apache License 2.0'.

Type Conversion:

The following images illustrates all possible type conversions regarding: SL, SLV, SLVV and SLM.