I was reading certain datasheets for GaN MOSFETs and came across manufacturers saying about achieving "Ultra Low Inductance". If I am correct, it has to do with increasing the trace width within the PCBs. This enables fast charging of the gate of a MOSFET. But, if the inductance is ultra-low, it would mean that the stray capacitance due to wider traces will be ultra-high? Am I correct?
In this case, if I am correct, wouldn't the higher capacitance interfere with the gate voltage?