For a sequential implementation, you just need a pair of counters that have "enable" inputs, and a small amount of additional logic.

^{simulate this circuit – Schematic created using CircuitLab}

Note that this circuit outputs 3 through 8 for valid inputs (and zero otherwise). If you want 2 through 7, you'll have to subtract one, or figure out a way to inhibit U2 from counting the first bit.

For a sequential implementation, you just need a pair of counters that have "enable" inputs, and a small amount of additional logic.

^{simulate this circuit – Schematic created using CircuitLab}

I've edited the circuit to add a missing gate (AND6). U1 counts the ones while U2 counts all the bits. U1 can be only 2 bits because it only needs to count to 3 (binary 11). U2 needs to be 4 bits because it needs to be able to count to 8 (see below). AND1 through AND4 force the output to zero if there aren't 3 ones in the data. This all pretty much follows from the problem description.

Note that this circuit outputs 3 through 8 for valid inputs (and zero otherwise). If you want 2 through 7, you'll have to subtract one, or figure out a way to inhibit U2 from counting the first bit.