This novel voltage reference was presented for sensing ferromagnetic RAM with a self-trimmed bias voltage reference Vre.

I ran it on Falstad's sim and found some novel properties.

1. Vre matches Vgs(th) of T1 plus the very low current and voltage drop across R2.
2. When R2 matches R3 then any noise in Vdd has a 98% reduction if both FETs are matched, which was the optimal R ratio point.
3. If T2 has a much lower Vgs(th) then the reduction is more than 99.6% reduced.

This puts both T1 and T2 into the saturation high resistance zone.

Read the Vpp levels.

This novel voltage reference was presented for sensing ferromagnetic RAM with a self-trimmed bias voltage reference Vre.

I ran it on Falstad's sim and found some novel properties.

1. Vre matches Vgs(th) of T1 plus the very low current and voltage drop across R2.
2. When R2 matches R3 then any noise in Vdd has a 98% reduction if both FETs are matched, which was the optimal R ratio point.
3. If T2 has a much lower Vgs(th) then the reduction is more than 99.6% reduced.

This puts both T1 and T2 into the saturation high resistance zone.

Read the Vpp levels.

In another simulation using R2/R1=50, I vary R3 and record Vref using V+=10V. But due to the heat loss at high Vref/V+, efficient low current occurs with low R3/R2 <<1 while R2/R1=50.

This novel voltage reference was presented for sensing ferromagnetic RAM with a self-trimmed bias voltage reference Vre.

I ran it on Falstad's sim and found some novel properties.

1. Vre matches Vgs(th) of T1 plus the very low current and voltage drop across R2.
2. When R2 matches R3 the the noise in Vdd has a 98% reduction if both FETs are matched which was the minimum point.
3. If T2 has a much lower Vgs(th) then the reduction is more than 99.6 reduced.

This puts both T1 and T2 into the saturation high resistance zone.  

This novel voltage reference was presented for sensing ferromagnetic RAM with a self-trimmed bias voltage reference Vre.

I ran it on Falstad's sim and found some novel properties.

1. Vre matches Vgs(th) of T1 plus the very low current and voltage drop across R2.
2. When R2 matches R3 then any noise in Vdd has a 98% reduction if both FETs are matched, which was the optimal R ratio point.
3. If T2 has a much lower Vgs(th) then the reduction is more than 99.6% reduced.

This puts both T1 and T2 into the saturation high resistance zone.

Read the Vpp levels.