UART.twr

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Release 14.7 Trace  (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml UART.twx UART.ncd -o UART.twr UART.pcf

Design file:              UART.ncd
Physical constraint file: UART.pcf
Device,package,speed:     xc3s400,ft256,-4 (PRODUCTION 1.39 2013-10-13)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
BTN_IN      |    1.064(R)|    0.618(R)|CLK_BUFGP         |   0.000|
RESET       |    3.658(R)|   -1.421(R)|CLK_BUFGP         |   0.000|
RX_in       |    1.870(R)|    1.216(R)|CLK_BUFGP         |   0.000|
TX_DATA<0>  |    0.863(R)|    0.778(R)|CLK_BUFGP         |   0.000|
TX_DATA<1>  |    1.146(R)|    0.553(R)|CLK_BUFGP         |   0.000|
TX_DATA<2>  |    0.875(R)|    0.769(R)|CLK_BUFGP         |   0.000|
TX_DATA<3>  |    0.549(R)|    1.030(R)|CLK_BUFGP         |   0.000|
TX_DATA<4>  |    1.182(R)|    0.524(R)|CLK_BUFGP         |   0.000|
TX_DATA<5>  |    0.538(R)|    1.038(R)|CLK_BUFGP         |   0.000|
TX_DATA<6>  |    0.693(R)|    0.914(R)|CLK_BUFGP         |   0.000|
TX_DATA<7>  |    0.788(R)|    0.839(R)|CLK_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
RX_DATA<0>  |    9.457(R)|CLK_BUFGP         |   0.000|
RX_DATA<1>  |    9.221(R)|CLK_BUFGP         |   0.000|
RX_DATA<2>  |    9.123(R)|CLK_BUFGP         |   0.000|
RX_DATA<3>  |    8.401(R)|CLK_BUFGP         |   0.000|
RX_DATA<4>  |    8.807(R)|CLK_BUFGP         |   0.000|
RX_DATA<5>  |    9.126(R)|CLK_BUFGP         |   0.000|
RX_DATA<6>  |    8.402(R)|CLK_BUFGP         |   0.000|
RX_DATA<7>  |    9.077(R)|CLK_BUFGP         |   0.000|
RX_NEWDATA  |    9.122(R)|CLK_BUFGP         |   0.000|
TX_OUT      |    9.100(R)|CLK_BUFGP         |   0.000|
TX_READY    |    8.417(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    6.251|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue Jul 09 08:51:25 2019 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 4491 MB