"asic_config_v3" - Add minipack3bta platform and its variants

Implements `asic_config_v3` design.

In this PR, add platform configurations for `minipack3bta`.

Author: marif-nexthop

fboss/lib/asic_config_v3/generators/broadcom_xgs_generator.py

@@ -5,6 +5,7 @@
 from typing import Any
 
 import yaml
+
 from fboss.lib.asic_config_v3.base_generator import BaseAsicConfigGenerator, MODULE_DIR
 from fboss.lib.platform_mapping_v2.gen import read_all_vendor_data
 from fboss.lib.platform_mapping_v2.platform_mapping_v2 import PlatformMappingParser
@@ -19,10 +20,7 @@ class BroadcomXgsGenerator(BaseAsicConfigGenerator):
     ASIC_FAMILY: str = "xgs"
 
     def __init__(
-        self,
-        platform_name: str,
-        variant: str,
-        platform_config: dict[str, Any],
+        self, platform_name: str, variant: str, platform_config: dict[str, Any]
     ) -> None:
         super().__init__(platform_name, variant, platform_config)
 
@@ -37,10 +35,14 @@ def __init__(
         self.num_ports_per_core: int = self.platform_config.get("num_ports_per_core", 2)
         self.mmu_size: int = self.asic_config.get("mmu_size", 9416)
 
-        # Compute lanes_per_port from ASIC port_architecture and platform num_ports_per_core
+        # lanes_per_port is derived from the ASIC port architecture unless the
+        # platform wires only a subset of chip lanes per port and overrides it
+        # explicitly via num_lanes_per_port.
         port_arch = self.asic_config.get("port_architecture", {})
         num_lanes_per_core = port_arch.get("num_lanes_per_core", 8)
-        self.lanes_per_port: int = num_lanes_per_core // self.num_ports_per_core
+        self.lanes_per_port: int = self.platform_config.get(
+            "num_lanes_per_port", num_lanes_per_core // self.num_ports_per_core
+        )
 
     @property
     def output_extension(self) -> str:
@@ -238,6 +240,10 @@ def _get_logical_port_to_physical_port_mapping(self) -> list[list[int]]:
           * ``lp_offset_simple``: when true, compute the per-port logical-port
             offset as ``i * lanes_per_port`` on all cores rather than using
             the default even / odd conditional.
+          * ``special_core_offset_apply_all``: special-case compat flag. When
+            true, apply the +1 core offset to every core rather than only
+            cores 0 and 1, to reproduce a platform's pre-existing linear-stride
+            mapping. The offset is only physically meaningful on cores 0/1.
         """
         port_arch = self.asic_config.get("port_architecture", {})
         port_mapping_overrides = self.variant_config.get("port_mapping_overrides", {})
@@ -254,12 +260,15 @@ def _get_logical_port_to_physical_port_mapping(self) -> list[list[int]]:
         lanes_per_core = port_arch.get("num_lanes_per_core", 8)
         lp_start_step_offset = port_mapping_overrides.get("lp_start_step_offset", 1)
         lp_offset_simple = port_mapping_overrides.get("lp_offset_simple", False)
+        special_core_offset_apply_all = port_mapping_overrides.get(
+            "special_core_offset_apply_all", False
+        )
 
         logical_to_physical_port_mapping = []
         cores = self._get_core_range()
 
         for core_num in cores:
-            core_offset = 1 if core_num <= 1 else 0
+            core_offset = 1 if (special_core_offset_apply_all or core_num <= 1) else 0
             lp_start_offset = 0 if core_num % 2 == 0 else lp_on_even_core
             lp_start = (
                 (core_num // 2) * (lp_per_dp + lp_start_step_offset)
@@ -407,10 +416,7 @@ def _generate_port_config(self, mgmt_port: bool = False) -> None:
                 port_ranges_str = ", ".join(port_ranges)
                 pc_key = (f"PORT_ID: [{port_ranges_str}]",)
 
-        self.values["PORT"][pc_key] = (
-            f"MTU: {self.mmu_size}",
-            "MTU_CHECK: 1",
-        )
+        self.values["PORT"][pc_key] = (f"MTU: {self.mmu_size}", "MTU_CHECK: 1")
 
     def _generate_device_config_overrides(self) -> None:
         """Apply device config overrides from variant config."""

fboss/lib/asic_config_v3/platforms/minipack3bta/asic_config.json

@@ -0,0 +1,46 @@
+{
+  "platform_name": "minipack3bta",
+  "vendor": "broadcom",
+  "asic": "tomahawk5",
+  "num_ports_per_core": 1,
+  "num_lanes_per_port": 4,
+  "defaults": {
+    "asic_config_params": {
+      "config_type": "YAML_CONFIG",
+      "exact_match": false,
+      "mmu_lossless": false,
+      "config_gen_type": "DEFAULT"
+    },
+    "port_config": {
+      "default_speed": 400000,
+      "speed_to_fec": {
+        "100000": "PC_FEC_RS544",
+        "400000": "PC_FEC_RS544_2XN"
+      }
+    },
+    "cpu_port": {
+      "speed": 10000,
+      "num_lanes": 1
+    },
+    "mgmt_port": {
+      "enabled": false
+    },
+    "port_mapping_overrides": {
+      "num_logical_ports_per_datapath": 8,
+      "lp_start_step_offset": 0,
+      "num_lp_ports_on_even_core": 4,
+      "special_core_offset_apply_all": true
+    },
+    "features": {
+      "generate_dlb_config": true,
+      "generate_autoload_board_settings": true
+    },
+    "ctr_eflex_config": {
+      "CTR_ING_EFLEX_OPERMODE_PIPEUNIQUE": 1,
+      "CTR_EGR_EFLEX_OPERMODE_PIPEUNIQUE": 1
+    }
+  },
+  "variants": {
+    "internal": {}
+  }
+}

fboss/lib/asic_config_v3/schemas/platform_config.schema.json

@@ -170,9 +170,9 @@
                             "type": "boolean",
                             "description": "When true, computes the per-port logical-port offset as i * lanes_per_port on all cores rather than using the default even / odd conditional."
                         },
-                        "core_offset_apply_all": {
+                        "special_core_offset_apply_all": {
                             "type": "boolean",
-                            "description": "When true, applies the +1 core offset to every core rather than only cores 0 and 1. Required for platforms with a linear-stride port layout."
+                            "description": "Special-case compat flag: when true, applies the +1 core offset to every core rather than only cores 0 and 1, to reproduce a platform's pre-existing linear-stride mapping. Only physically meaningful on cores 0/1."
                         }
                     }
                 },