[system_integration] move libero setup to neorv32-setups repository

Author: stnolting

docs/legal.adoc

@@ -63,7 +63,6 @@ POSSIBILITY OF SUCH DAMAGE.
 * "ARM", "AMBA", "AXI", "AXI4", "AXI4-Lite" and "AXI4-Stream" are trademarks of Arm Holdings plc.
 * "ModelSim" is a trademark of Mentor Graphics – A Siemens Business.
 * "Quartus [Prime]" and "Cyclone" are trademarks of Intel Corporation.
-* "Libero" and "PolarFire" are trademarks of Microchip Technology Incorporated.
 * "iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
 * "GateMate" is a trademark of Cologne Chip AG.
 * "Windows" is a trademark of Microsoft Corporation.

rtl/system_integration/README.md

@@ -29,14 +29,3 @@ This wrapper uses the `xbus2axi4_bridge.vhd` to convert the processor's XBUS pro
 > See the user guide's [UG: Packaging the Processor as Vivado IP Block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block)
 section for more information and step-by-step instructions for generating a NEORV32 IP module.
 
-### > `neorv32_libero_ip.vhd`
-
-Processor top entity with optional AXI4 and AXI4-Stream interfaces. Dedicated for integration as custom
-IP block within Microchip Libero. Run the provided 'neorv32_libero_ip.tcl' script in Libero after 
-importing the RTL to generate a NEORV32 HDL+ core.
-
-This wrapper uses the `xbus2axi4_bridge.vhd` to convert the processor's XBUS protocol into the AXI4 protocol.
-
-> [!NOTE]
-> BOOT_ADDR_CUSTOM and OCD_JEDEC_ID are not currently supported in the HDL+ core configurator and should be 
-set in the 'neorv32_libero_ip.vhd' top file when using the SmartDesign flow.