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Rev

3

A cool piece of news. If this works universally on either of the Intel, AMD, ARM, ... architectures, then the code re-design was indeed a brilliant move. If the trick was to just use the new possibilities, coming from hardware-based extended registers and vectorised operations instructions, not present on other processor architectures, the ARM and might be also the AMD ports will not enjoy the performance that you have enjoyed to observe. Anyway, enjoy the new powers available for further expanding your valued research.

user3666197
– user3666197

2017-12-15 11:51:49 +00:00
Commented Dec 15, 2017 at 11:51
1

Thank you for pointing me to this! I have forwarded a link to the Numba team for their encouragement.

Michael Grant
– Michael Grant

2017-12-16 19:42:35 +00:00
Commented Dec 16, 2017 at 19:42
2

@MichaelGrant I have a question for you, if you don't mind. Do you know if Numba provides a way to specify the "chunk size" when using prange() to parallelize a for-loop?

littleO
– littleO

2017-12-18 12:44:36 +00:00
Commented Dec 18, 2017 at 12:44
2

Thinking about it more, it makes sense that A * x would be slower in MATLAB than A' * x. With CSC storage, A' * x, is much easier to parallelize, because each row gets its own thread.

Michael Grant
– Michael Grant

2017-12-18 16:34:36 +00:00
Commented Dec 18, 2017 at 16:34
1

@GeoffreyNegiar I was hesitant to accept my own answer and to undo acceptance on a different answer, but you are right. I just made this the accepted answer.

littleO
– littleO

2020-06-18 19:08:08 +00:00
Commented Jun 18, 2020 at 19:08

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Correct minor typos or mistakes
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