Pads on multilayer PCBs

Normally, unconnected pads are removed. If your software doesn't do this automatically (or you disable it), you may be asked by the fabricator, and then you can decide if they should remove them for you, or build as given. Or they may remove them without asking at all.

They are normally removed because the extra features introduce more stress points which can fracture the hole's copper lining ("barrel").

Mind that, most EDA software shows all layers in the normal view, and compute clearance and connectivity accordingly. This can lead to anomalously high clearances to inner layers, when you consider that the pad gets removed in the end -- clearance which could be useful at times, if it were computed against the hole instead. Example: a grid of thermal vias, connecting to the exposed pad of a DFN or LGA type component, on a multilayer board where the inner layers (planes/pours) also need to fill under the component. For certain via spacings and clearances, the pour may be too thin, or disconnect completely, due to those vias.

One can set inner layer pad sizes to optimize this situation. For example in Altium, setting pad stack mode Top-Mid-Bottom, and setting the inner pad size to the hole diameter or a little bigger. (A little bigger may be desirable, as one needs to keep in mind the layer registration plus drill target tolerances add up: typically a hole-to-inner-copper clearance is larger than a hole-to-pad-edge (annular ring) dimension, so don't be too strict with this trick. Or, set pad size to hole size or less, and also set an inner layer clearance design rule, to the same end.)

Example:

Notice the G2 via has regular dimensions and clearance. Compare with the stitching/thermal vias which have reduced mid pads. Note the red arrow showing the minimum web width for the mid pour clearing the vias.

Curiously, the Gerber output shows it does not necessarily remove the inner layer pads:

This may be a minor bug with the old version Altium I use; it seems to determine "connectivity" based on traces touching the pad/via centers, and doesn't remove completely "unconnected" pads (probably out of an abundance of caution, because traces touching the center aren't the only way to connect a pad). Although there's nothing "connecting" that other removed pad, hmm, that's weird.

Checking the physical PCB sample (made by a common Chinese proto fab), I think they removed the pads unprompted, anyway.

In summary, there may be reasons to set these manually, but for the most part, they can be left alone, and either the EDA tool, or the fab, will handle them appropriately.