Advanced Architecture Research Group UNIMORE

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axi axi Public

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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog
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The multi-core cluster of a PULP system.

SystemVerilog

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richie-docs Public Forked from gbellocchi/richie-docs

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richie-cluster Public Forked from pulp-platform/pulp_cluster
The multi-core cluster of a PULP system.

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SystemVerilog 0 33 0 0 Updated Mar 25, 2025
axi Public Forked from pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

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SystemVerilog 0 340 0 0 Updated Dec 6, 2024

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