t8010: add H9P PCIe NVMe storage support by Pauli1Go · Pull Request #4 · HoolockLinux/linux

Pauli1Go · 2026-06-28T22:54:21Z

Add internal storage support for Apple A10/T8010 devices using the H9P PCIe
storage path. Tested on iPad7,12.

This adds:

apple,t8010-pcie binding
H9P PCIe host bridge driver
iPad7/J172 PCIe, DART and NVMMU DT description
H9P FlatDMA/NVMMU setup for the internal storage port
H9P-specific nvme-pci glue in pci-apple-h9p.c

The endpoint enumerates as PCIe NVMe, so this keeps using nvme-pci instead of
pretending it is an ANS/nvme-apple controller. The small private DMA hook is
needed because H9P uses non-standard per-request FlatDMA/NVMMU mapping.

Tested on iPad7,12:

boots Debian from internal /dev/nvme0n1p2
rootfs mounts read-write
SSH and graphical target start
512 MiB write smoke test passed
parallel write smoke test passed

Drop the temporary T8010 DART driver. The Hoolock base now has S5L8960X/T8010 support in apple-dart, so the iPad7 PCIe DART can use the upstream compatible fallback plus apple,dma-range. Move the Apple H9P FlatDMA helpers out of the main nvme-pci body into a private include file. The remaining pci.c changes are limited to the H9P hooks that still need private nvme-pci access. Signed-off-by: Pauli1Go <101004482+Pauli1Go@users.noreply.github.com>

Build the Apple H9P FlatDMA glue as a normal nvme-pci object instead of including a .c file from pci.c. Add a small internal dma_ops hook table so the remaining H9P integration points are explicit and generic. Remove the direct PMGR regmap power forcing from the H9P PCIe host. The live iPad7 boot now relies on the attached genpd power domains and still enumerates the Apple NVMe endpoint. Name the remaining PCIe/PHY bring-up constants used by the H9P port setup sequence, keeping the tested register sequence unchanged. Signed-off-by: Pauli1Go <101004482+Pauli1Go@users.noreply.github.com>

t8010 NVMe support

asdfugil · 2026-06-29T13:11:18Z

echo 1 > /sys/class/nvme/nvme0/reset_controller seems to be broken.

asdfugil · 2026-06-29T13:43:40Z

changed the base branch to a snapshot of 7.1 to facilitate review

asdfugil

The sign offs are invalid. You must sign off using a "known identity" and a real email.
https://docs.kernel.org/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin

Please split up the commits properly, in this order

Add PCIE device tree bindings
Add PCIE driver
Add NVME Glue
Update DTS
Update MAINTAINERS file (ARM/APPLE MACHINE SUPPORT section)

Reset nvme controller seems to be broken, it should however be fixable and made to work.

You should also look into if the changes could be added to pcie-apple.c instead. That being said, I do not know enough about the pcie controller to say for certain it is a better way.

I mentioned some things should be done by m1n1, so you need to prepare a m1n1 PR as well.

Check the git history of the file/directory for good commit title styles.
In order for me to try to merge this at all, you also need to commit to maintaining the driver and work to upstream the kernel changes.

asdfugil · 2026-06-29T13:45:38Z

+		};
+	};
+
+	soc {


everything here in soc {} belongs to t8010.dtsi, not here.

asdfugil · 2026-06-29T13:52:48Z

+		pcie0_nvmmu_window: nvmmu-window@8bee00000 {
+			reg = <0x8 0xbee00000 0x0 0x01200000>;
+			no-map;
+		};


this part goes into t8010-common.dtsi.

This part should be made to be filled by bootloader (m1n1) based on /arm-io/nvme-mmu0 in ADT,
make sure you have a /* To be filled by loader */ comment.

This memory region is for the NVMe controller's private use, so the name should be based on that, perhaps nvme-hmb@0? (0 because filled by loader)
Use an alias like nvme_hmb in the aliases node to make it easier for the loader to get the node.

asdfugil · 2026-06-29T13:55:50Z

+      Four port state interrupts followed by 32 MSI interrupts and the
+      optional NVMMU fault interrupt for the active storage port.
+    minItems: 37
+    maxItems: 37


maxItems without minItems implies identical minItems, so minItems here should be removed

also for clocks, clock-names, power-domains

asdfugil · 2026-06-29T13:56:48Z

+title: Apple H9P/T8010 PCIe Host Controller
+
+maintainers:
+  - Hector Martin <marcan@marcan.st>


No. Please do not lie about maintainer.

asdfugil · 2026-06-29T14:04:37Z

+
+  memory-region:
+    description:
+      Reserved physical window programmed into the H9P NVMMU/SART path.


This should be prefixed with apple,. I believe apple,nvme-hmb is a more appropriate name combined with above reviews.

When a node is referencing another node, please word like this in the description, Phandle of <another node description>

asdfugil · 2026-06-29T14:41:40Z

+	{ 0x013c, 4, 0x00000002, 0x00000002 },
+	{ 0x0140, 4, 0x0073ffff, 0x00704c4b },
+};
+


Tunables don't belong here. They should be applied in m1n1. (check the tunables properties in the ADT node)

asdfugil · 2026-06-29T14:44:23Z

+		dma_addr_t tcb_dma;
+		dma_addr_t tcb_table_dma;
+		dma_addr_t tcb_sgl_dma;
+	} nvmmu[H9P_NUM_PORTS];


Isn't nvmmu port0 only?

asdfugil · 2026-06-29T14:54:14Z

+		pcie0: pcie@610000000 {
+			compatible = "apple,t8010-pcie";
+			device_type = "pci";
+			status = "okay";


Don't use status unless it is disabled in a .dtsi file but is overriden to okay in another file.

asdfugil · 2026-06-29T14:56:32Z

+    items:
+      - const: config
+      - const: phy0
+      - const: phy1


There is only one phy, so this needs a better name. I believe this range corresponds to phy_base in m1n1's reg info, so maybe name this phy.

asdfugil · 2026-06-29T15:00:45Z

+      - const: config
+      - const: phy0
+      - const: phy1
+      - const: phy2


There is only one phy, so this needs a better name. I believe this range corresponds to phyip_base in m1n1's reg info, so maybe name this phy-ip.

asdfugil · 2026-06-30T16:30:31Z

+  interrupts:
+    description:
+      Four port state interrupts followed by 32 MSI interrupts and the
+      optional NVMMU fault interrupt for the active storage port.


Please use msi-ranges like in pcie-apple.c to specify a range of interrupts instead of writing out 32 consecutive interrupts.

yhavry · 2026-06-30T22:53:16Z

Currently only works when booting through PongoOS. The iBoot/remote_boot path does not leave the S3E/NVMe BAR/core initialized the same way, so CAP/scratch/core registers stay dead and NVMe probe fails. This also needs to be fixed. (iPhone 7 D101)

Pauli1Go added 4 commits June 28, 2026 22:52

apple: t8010: add clean H9P NVMe storage

5d758f1

Merge pull request #2 from Pauli1Go/dev

da05513

t8010 NVMe support

asdfugil force-pushed the hoolock branch from 1d28075 to 6375dd0 Compare June 29, 2026 09:56

asdfugil changed the base branch from hoolock to tests/adp June 29, 2026 13:42

asdfugil changed the base branch from tests/adp to snapshot/hoolock-7.1-dart June 29, 2026 13:42

asdfugil requested changes Jun 29, 2026

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t8010: add H9P PCIe NVMe storage support#4

t8010: add H9P PCIe NVMe storage support#4
Pauli1Go wants to merge 4 commits into
HoolockLinux:snapshot/hoolock-7.1-dartfrom
Pauli1Go:hoolock

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+              		};
+              	};
+              	soc {

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