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1. riscv-soc-uart riscv-soc-uart Public

   A simple 32-bit RISC-V (RV32I) CPU core and SoC in Verilog with a memory-mapped UART.

   Verilog 2 2

2. adaptive-rnn-channel-equalizer-on-fpga adaptive-rnn-channel-equalizer-on-fpga Public

   GRU-based neural network equalizer in Verilog with FPGA deployment, RTL simulation, and on-chip BPTT training for adaptive communication channel equalization.

   Verilog 1

3. Custom-Quadcopter-Flight-Controller Custom-Quadcopter-Flight-Controller Public

   Custom flight controller for STM32F407 using MPU6050 and PID control with Kalman Filter

   C 1 1

4. tiny-yolo-hardware-accelerator tiny-yolo-hardware-accelerator Public

   Verilog implementation of a CNN-style image processing pipeline with convolution, activation, pooling, and RTL-based verification.

   Verilog 1

5. riscv-pipelined-processor riscv-pipelined-processor Public

   5-stage pipelined RV32I processor in Verilog featuring hazard detection, forwarding, and RTL simulation-based verification.

   Verilog

6. Design-of-Async-FIFO-with-UVM-Style-Verification Design-of-Async-FIFO-with-UVM-Style-Verification Public

   A parameterizable Asynchronous FIFO RTL design verified using a custom UVM-style Object-Oriented testbench. Features 100% functional coverage, cycle-accurate timing, and SystemVerilog Assertions (S…

   SystemVerilog 1