# Hi 👋, I'm Tavakalmastan

## 🚀 ASIC Physical Design | RTL-to-GDSII | STA | CTS | P&R

Electronics & Communication Engineering graduate focused on **ASIC Physical Design and Backend VLSI**, with hands-on experience in **RTL-to-GDSII implementation using Cadence Genus and Innovus**.

- 🎓 **B.E. Electronics & Communication Engineering — 2026**
- 📊 **CGPA: 8.44**
- 🏢 **ASIC Physical Design Trainee — VLSIMINDS**
- 💼 **Former ASIC Physical Design Intern — VLSIMINDS**
- 📍 **Bengaluru, India**

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## 💼 Physical Design Experience

### ASIC Physical Design Trainee

**VLSIMINDS — A Division of S2C Semiconductor Pvt. Ltd.**  
**June 2026 – Present | Bengaluru**

Currently undergoing advanced **ASIC Physical Design training** focused on:

- ASIC Physical Design Flow, Netlist, SDC, Libraries & Technology Files
- TLU+, UPF & Physical Design Inputs
- STA: Setup/Hold, Latency, Skew & Uncertainty
- Timing Paths/Arcs, Recovery/Removal & Multi-Cycle Paths
- Timing Bottleneck Analysis, Crosstalk, Multi-Vt Cells & Timing Closure
- Blockages & Electromigration

### ASIC Physical Design Intern

**VLSIMINDS — A Division of S2C Semiconductor Pvt. Ltd.**  
**February 2026 – May 2026 | Bengaluru**

- Executed **RTL-to-GDSII flow** using Cadence Genus & Innovus
- Worked on **Floorplanning, Placement, CTS, Routing & STA**
- Implemented **SRAM Controller & ChipTop designs on 45nm**
- Performed **DRC, Timing, Congestion & QoR Optimization**
- Automated report generation using **TCL scripting**

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## 🔬 Featured Projects

### ChipTop ASIC Physical Design — 45nm

**Cadence Innovus | Netlist-to-GDSII**

- Complete Physical Design flow from Floorplanning to Routing & Timing Analysis
- Reduced **DRC violations from 11 → 0**
- Achieved **zero connectivity violations**

### SRAM Controller ASIC Design — 45nm

**Cadence Genus & Innovus | RTL-to-GDSII**

- Complete RTL-to-GDSII implementation
- Resolved approximately **7,800 DRC violations**
- Worked on **Setup/Hold timing closure and physical optimization**

### FIFO ASIC Physical Design

**Cadence Innovus | RTL-to-GDSII**

- Floorplanning, Placement, CTS, Routing & Timing Analysis

### ALU16 PPA Optimization

**OpenLane | Sky130**

- RTL-to-GDSII implementation with PPA analysis

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## 🛠️ Technical Skills

**Physical Design:**  
RTL-to-GDSII, Floorplanning, Placement, CTS, Routing, Timing Closure, DRC, QoR Optimization

**STA:**  
Setup/Hold, Timing Paths & Arcs, Latency, Skew, Uncertainty, Recovery/Removal, Crosstalk

**EDA Tools:**  
Cadence Innovus, Cadence Genus, Cadence Virtuoso, OpenLane, PrimeTime (Learning)

**Scripting & Programming:**  
TCL, Python, Verilog HDL, C (Basic)

**Environment:**  
Linux, GVim, Git, GitHub

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## 🎓 Education

### Bachelor of Engineering — Electronics & Communication Engineering

**Acharya Institute of Technology, Bengaluru**  
**2022 – 2026 | CGPA: 8.44**

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## 🏆 Certifications & Activities

- **NPTEL — VLSI Design Flow: RTL to GDS**
- **Digital IC Design using Cadence Tools — C2S Programme**
- **Memory Design & Verification using Verilog — C2S Programme**
- **Participant — VEDAS 2026 International Conference**

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## 🎯 Open to Work

Currently looking for **entry-level ASIC Physical Design / Backend VLSI opportunities**.

**Interested in:**  
ASIC Physical Design | P&R | STA | CTS | Timing Closure | RTL-to-GDSII

📍 **Preferred Locations:** Bengaluru / Hyderabad

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## 🌐 Connect With Me

🔗 [LinkedIn](https://www.linkedin.com/in/tavakalmastan)  
🔗 [GitHub](https://github.com/Tavakalmastan)

⭐ Thanks for visiting my profile!