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fby3.5: common: Delay ready time#251

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fby3.5: common: Delay ready time#251
DelphineChiu wants to merge 1 commit into
facebook:main_v2from
Wiwynn:Sara/main2_fby3.5-Delay_bic_ready

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fby3.5: common: Delay ready time
Summary:

  • Check sensor polling once before BIC pulls ready GPIO high.
    To avoid BMC too early to ask for any pieces of information.

Test plan

  • Build code: Pass
  • Ready pin is delay: Pass

Log:

  1. Check BIC ready GPIO is delay.
  • Before: Due to didn't check sensor reading, BIC ready value changed too fast to get different.
    root@bmc-oob:~# fw-util slot1 --force --update bic oby35-cl-2022.13.01.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
    slot_id: 1, comp: 2, intf: 0, img: oby35-cl-2022.13.01.bin, force: 1
    Set fan mode to manual and set PWM to 70%
    file size = 327680 bytes, slot = 1, intf = 0xff
    updating fw on slot 1:
    updated bic: 100 %
    Elapsed time: 20 sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar 9 04:37:43 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:46 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:37:49 PST 2018
9C 9C 00 1C 01

  • After: Due to checking sensor are polling once, we can get BIC ready value change.
    root@bmc-oob:~# fw-util slot1 --force --update bic Y35BCL.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
    slot_id: 1, comp: 2, intf: 0, img: Y35BCL.bin, force: 1
    Set fan mode to manual and set PWM to 70%
    file size = 296440 bytes, slot = 1, intf = 0xff
    updating fw on slot 1:
    updated bic: 100 %
    Elapsed time: 18 sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar 9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:38:22 PST 2018
9C 9C 00 1C 00
Fri Mar 9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar 9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar 9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar 9 04:38:25 PST 2018
9C 9C 00 1C 01

@facebook-github-bot facebook-github-bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Apr 20, 2022
@DelphineChiu

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Dependency: #250

@SaraSYLin SaraSYLin force-pushed the Sara/main2_fby3.5-Delay_bic_ready branch from 1edb7ae to 0083af1 Compare April 20, 2022 06:14
@SaraSYLin

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Hi @GoldenBug ,
Force update to rebase main_v2.
Please help to review again, thank you.

@facebook-github-bot

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@GoldenBug has imported this pull request. If you are a Meta employee, you can view this diff on Phabricator.

Comment thread common/lib/util_sys.c
Comment thread common/lib/util_sys.c
Comment thread common/sensor/sensor.c Outdated
Comment thread common/sensor/sensor.c Outdated
Summary:
- Check sensor polling once before BIC pulls ready GPIO high.
To avoid BMC too early to ask for any pieces of information.

Test plan
- Build code: Pass
- Ready pin is delay: Pass

Log:
1. Check BIC ready GPIO is delay.
- Before: Due to didn't check sensor reading, BIC ready value changed too fast to get different.
root@bmc-oob:~# fw-util slot1 --force --update bic oby35-cl-2022.13.01.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
slot_id: 1, comp: 2, intf: 0, img: oby35-cl-2022.13.01.bin, force: 1
Set fan mode to manual and set PWM to 70%
file size = 327680 bytes, slot = 1, intf = 0xff
updating fw on slot 1:
updated bic: 100 %
Elapsed time:  20   sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar  9 04:37:43 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:46 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:49 PST 2018
9C 9C 00 1C 01

- After: Due to checking sensor are polling once, we can get BIC ready value change.
root@bmc-oob:~# fw-util slot1 --force --update bic Y35BCL.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
slot_id: 1, comp: 2, intf: 0, img: Y35BCL.bin, force: 1
Set fan mode to manual and set PWM to 70%
file size = 296440 bytes, slot = 1, intf = 0xff
updating fw on slot 1:
updated bic: 100 %
Elapsed time:  18   sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar  9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:22 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:25 PST 2018
9C 9C 00 1C 01
@SaraSYLin SaraSYLin force-pushed the Sara/main2_fby3.5-Delay_bic_ready branch from 0083af1 to a4f4d9f Compare April 22, 2022 01:28
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@DelphineChiu has updated the pull request. You must reimport the pull request before landing.

@SaraSYLin

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Hi @GoldenBug ,
Thanks for your comments.
Based on your suggestions to modify the code and force update this branch.
Please help review it again, thank you.

@GoldenBug

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Looks good to me!

@GoldenBug GoldenBug closed this Apr 22, 2022
facebook-github-bot pushed a commit that referenced this pull request Apr 22, 2022
Summary:
fby3.5: common: Delay ready time

- Check sensor polling once before BIC pulls ready GPIO high.
To avoid BMC too early to ask for any pieces of information.

Pull Request resolved: #251

Test Plan:
- Build code: Pass
- Ready pin is delay: Pass

Log:
1. Check BIC ready GPIO is delay.
- Before: Due to didn't check sensor reading, BIC ready value changed too fast to get different.
root@bmc-oob:~# fw-util slot1 --force --update bic oby35-cl-2022.13.01.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
slot_id: 1, comp: 2, intf: 0, img: oby35-cl-2022.13.01.bin, force: 1
Set fan mode to manual and set PWM to 70%
file size = 327680 bytes, slot = 1, intf = 0xff
updating fw on slot 1:
updated bic: 100 %
Elapsed time:  20   sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar  9 04:37:43 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:46 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:49 PST 2018
9C 9C 00 1C 01

- After: Due to checking sensor are polling once, we can get BIC ready value change.
root@bmc-oob:~# fw-util slot1 --force --update bic Y35BCL.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
slot_id: 1, comp: 2, intf: 0, img: Y35BCL.bin, force: 1
Set fan mode to manual and set PWM to 70%
file size = 296440 bytes, slot = 1, intf = 0xff
updating fw on slot 1:
updated bic: 100 %
Elapsed time:  18   sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar  9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:22 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:25 PST 2018
9C 9C 00 1C 01

Reviewed By: garnermic

Differential Revision: D35820076

Pulled By: GoldenBug

fbshipit-source-id: 9257f04ce67e08cc931a96e94f1d98cdd42d8184
facebook-github-bot pushed a commit that referenced this pull request Apr 26, 2022
Summary:
fby3.5: common: Delay ready time

- Check sensor polling once before BIC pulls ready GPIO high.
To avoid BMC too early to ask for any pieces of information.

Pull Request resolved: #251

Test Plan:
- Build code: Pass
- Ready pin is delay: Pass

Log:
1. Check BIC ready GPIO is delay.
- Before: Due to didn't check sensor reading, BIC ready value changed too fast to get different.
root@bmc-oob:~# fw-util slot1 --force --update bic oby35-cl-2022.13.01.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
slot_id: 1, comp: 2, intf: 0, img: oby35-cl-2022.13.01.bin, force: 1
Set fan mode to manual and set PWM to 70%
file size = 327680 bytes, slot = 1, intf = 0xff
updating fw on slot 1:
updated bic: 100 %
Elapsed time:  20   sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar  9 04:37:43 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:44 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:45 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:46 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:47 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:48 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:37:49 PST 2018
9C 9C 00 1C 01

- After: Due to checking sensor are polling once, we can get BIC ready value change.
root@bmc-oob:~# fw-util slot1 --force --update bic Y35BCL.bin; while [ 1 ]; do date; bic-util slot1 0xe0 0x41 0x9c 0x9c 0x0 0x0 28; sleep 0.5; done;
slot_id: 1, comp: 2, intf: 0, img: Y35BCL.bin, force: 1
Set fan mode to manual and set PWM to 70%
file size = 296440 bytes, slot = 1, intf = 0xff
updating fw on slot 1:
updated bic: 100 %
Elapsed time:  18   sec.

Set fan mode to auto and start fscd
Force upgrade of slot1 : bic succeeded
Fri Mar  9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:21 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:22 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:23 PST 2018
9C 9C 00 1C 00
Fri Mar  9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:24 PST 2018
9C 9C 00 1C 01
Fri Mar  9 04:38:25 PST 2018
9C 9C 00 1C 01

Reviewed By: garnermic

Differential Revision: D35941609

Pulled By: GoldenBug

fbshipit-source-id: e077fb3cd967a6ef692bca0d8b71f44c97518983
@SaraSYLin SaraSYLin deleted the Sara/main2_fby3.5-Delay_bic_ready branch May 5, 2022 05:35
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