fby3.5: cl:Increase the I2C clock rate accuracy

[DelphineChiu]

Summary:

• The clock rate of I2C bus-1/3/4 is set as 100kHz in DTS(overlay) file.
  The real clock rate(around 103kHz) is higher than 100kHz because of the AST I2C clock divider setting.
  This doesn't meet hardware's critera.
  The hardware's critera is the real clock rate should be lower than the clock rate that BIC set.
  So, BIC increases the I2C clock rate accuracy in Zephyr Kernel.
  After the modifaction, the real clock rate is around 92MHz.

Test Plan:

1. Check the I2C clock rate - pass
   Log:
   uart:$ md 0x7e6e2200 1
   [7e6e2200] 00000000 --> H-PLL = 1000MHz
   uart:$ md 0x7e6e2310 1
   [7e6e2310] 43f90900 --> PCLK = 50MHz
   uart:$ md 0x7e7b0010 1
   [7e7b0010] 62220803 --> base_divider_1 = 20MHz, base_divider_2 = 10MHz, base_divider_3 = 2.77MHz, base_divider_4 = 1MHz
   [Bus 0 - is set as 400kHz in DTS]
   uart:$ md 0x7e7b0084 1
   [7e7b0084] 009ad002 --> clock rate = 10M/(25) = 400kHz
   [Bus 1 - is set as 100kHz in DTS]
   uart:$ md 0x7e7b0104 1
   [7e7b0104] 00bce003 --> clock rate = 2.77M/28 = 99.2kHz
   [Bus 2 - is set as 1MHz in DTS]
   uart:$ md 0x7e7b0184 1
   [7e7b0184] 0078a001 --> clock rate = 20M/20 = 1MHz

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