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fby3.5: rf: Support power sequence#311

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Wiwynn:Sara/fby3.5-rf-Support_power_sequence
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fby3.5: rf: Support power sequence#311
DelphineChiu wants to merge 1 commit into
facebook:mainfrom
Wiwynn:Sara/fby3.5-rf-Support_power_sequence

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Summary:

  • Support power on/off sequence of CXL controller and device.
  • When power on/off failed, send SEL to BMC and close the power.

Test plan:

  • Build code: Pass
  • Power on CXL: Pass
  • Power off CXL: Pass
  • Send SEL: Pass

Log:

  1. Check CXL pwoer on successfully.
    [BIC console]
    [set_MB_DC_status] gpio number(32) status(1)
    [set_DC_status] gpio number(33) status(0)
    uart:~$ [control_power_on_sequence] power on success

uart:~$ platform gpio list_all
...
[27 ] PVPP_CD_PG_R : PP | input (I) | 1(1)
[28 ] P0V8_ASICA_PWRGD : PP | input (I) | 1(1)
[29 ] PVTT_AB_PG_R : PP | input (I) | 1(1)
[31 ] PVTT_CD_PG_R : PP | input (I) | 1(1)
[33 ] PWRGD_CARD_PWROK : PP | output(O) | 1(1)
[43 ] P0V9_ASICA_PWRGD : PP | input (I) | 1(1)
[44 ] P1V8_ASIC_PG_R : PP | input (I) | 1(1)
[49 ] PVPP_AB_PG_R : PP | input (I) | 1(1)
[53 ] P0V8_ASICD_PWRGD : PP | input (I) | 1(1)
[54 ] PWRGD_PVDDQ_CD : PP | input (I) | 1(1)
[59 ] PWRGD_PVDDQ_AB : PP | input (I) | 1(1)
...

  1. Check CXL power off successfully.
    uart:~$ [set_MB_DC_status] gpio number(32) status(0)
    [control_power_off_sequence] power off success

uart:~$ platform gpio list_all
...
[27 ] PVPP_CD_PG_R : PP | input (I) | 0(0)
[28 ] P0V8_ASICA_PWRGD : PP | input (I) | 0(0)
[29 ] PVTT_AB_PG_R : PP | input (I) | 0(0)
[31 ] PVTT_CD_PG_R : PP | input (I) | 0(0)
[33 ] PWRGD_CARD_PWROK : PP | output(O) | 0(0)
[43 ] P0V9_ASICA_PWRGD : PP | input (I) | 0(0)
[44 ] P1V8_ASIC_PG_R : PP | input (I) | 0(0)
[49 ] PVPP_AB_PG_R : PP | input (I) | 0(0)
[53 ] P0V8_ASICD_PWRGD : PP | input (I) | 0(0)
[54 ] PWRGD_PVDDQ_CD : PP | input (I) | 0(0)
[59 ] PWRGD_PVDDQ_AB : PP | input (I) | 0(0)
...

  1. Check can send SEL when power on or off failed.
    root@bmc-oob:~# log-util --print all
    ...
    2 slot2 2022-05-23 22:01:18 ipmid SEL Entry: FRU: 2, Record: Standard (0x02), Time: 2022-05-23 22:01:18, Sensor: PWR_ERR (0x56), Event Data: (030A0A) EXP PWROK Failure Assertion
    2 slot2 2022-05-23 22:01:18 ipmid SEL Entry: FRU: 2, Record: Standard (0x02), Time: 2022-05-23 22:01:18, Sensor: PWR_ERR (0x56), Event Data: (04030A) EXP PWROFF Failure Assertion
@facebook-github-bot facebook-github-bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label May 31, 2022
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@GoldenBug has imported this pull request. If you are a Meta employee, you can view this diff on Phabricator.

Summary:
- Support power on/off sequence of CXL controller and device.
- When power on/off failed, send SEL to BMC and close the power.

Test plan:
- Build code: Pass
- Power on CXL: Pass
- Power off CXL: Pass
- Send SEL: Pass

Log:
1. Check CXL pwoer on successfully.
[BIC console]
[set_MB_DC_status] gpio number(32) status(1)
[set_DC_status] gpio number(33) status(0)
uart:~$ [control_power_on_sequence] power on success

uart:~$ platform gpio list_all
...
[27 ] PVPP_CD_PG_R                       : PP  | input (I) | 1(1)
[28 ] P0V8_ASICA_PWRGD                   : PP  | input (I) | 1(1)
[29 ] PVTT_AB_PG_R                       : PP  | input (I) | 1(1)
[31 ] PVTT_CD_PG_R                       : PP  | input (I) | 1(1)
[33 ] PWRGD_CARD_PWROK                   : PP  | output(O) | 1(1)
[43 ] P0V9_ASICA_PWRGD                   : PP  | input (I) | 1(1)
[44 ] P1V8_ASIC_PG_R                     : PP  | input (I) | 1(1)
[49 ] PVPP_AB_PG_R                       : PP  | input (I) | 1(1)
[53 ] P0V8_ASICD_PWRGD                   : PP  | input (I) | 1(1)
[54 ] PWRGD_PVDDQ_CD                     : PP  | input (I) | 1(1)
[59 ] PWRGD_PVDDQ_AB                     : PP  | input (I) | 1(1)
...

2. Check CXL power off successfully.
uart:~$ [set_MB_DC_status] gpio number(32) status(0)
[control_power_off_sequence] power off success

uart:~$ platform gpio list_all
...
[27 ] PVPP_CD_PG_R                       : PP  | input (I) | 0(0)
[28 ] P0V8_ASICA_PWRGD                   : PP  | input (I) | 0(0)
[29 ] PVTT_AB_PG_R                       : PP  | input (I) | 0(0)
[31 ] PVTT_CD_PG_R                       : PP  | input (I) | 0(0)
[33 ] PWRGD_CARD_PWROK                   : PP  | output(O) | 0(0)
[43 ] P0V9_ASICA_PWRGD                   : PP  | input (I) | 0(0)
[44 ] P1V8_ASIC_PG_R                     : PP  | input (I) | 0(0)
[49 ] PVPP_AB_PG_R                       : PP  | input (I) | 0(0)
[53 ] P0V8_ASICD_PWRGD                   : PP  | input (I) | 0(0)
[54 ] PWRGD_PVDDQ_CD                     : PP  | input (I) | 0(0)
[59 ] PWRGD_PVDDQ_AB                     : PP  | input (I) | 0(0)
...

3. Check can send SEL when power on or off failed.
root@bmc-oob:~# log-util --print all
...
2    slot2    2022-05-23 22:01:18    ipmid            SEL Entry: FRU: 2, Record: Standard (0x02), Time: 2022-05-23 22:01:18, Sensor: PWR_ERR (0x56), Event Data: (030A0A) EXP PWROK Failure Assertion
2    slot2    2022-05-23 22:01:18    ipmid            SEL Entry: FRU: 2, Record: Standard (0x02), Time: 2022-05-23 22:01:18, Sensor: PWR_ERR (0x56), Event Data: (04030A) EXP PWROFF Failure Assertion
@SaraSYLin SaraSYLin force-pushed the Sara/fby3.5-rf-Support_power_sequence branch from 9a5f1cc to a11b13a Compare June 2, 2022 08:43
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@DelphineChiu has updated the pull request. You must reimport the pull request before landing.

@SaraSYLin

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Hi @GoldenBug ,
Force update to rebase main.
Please help to review again, thank you.

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@GoldenBug has imported this pull request. If you are a Meta employee, you can view this diff on Phabricator.

@SaraSYLin SaraSYLin deleted the Sara/fby3.5-rf-Support_power_sequence branch June 9, 2022 03:38
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