fby3.5: rf: Modify ASIC GPIO default

[DelphineChiu]

Summary:

• Modify ASIC GPIO default direction and value to follow EE release GPIO table.
  2 GPIOA2 ASIC_PERST1_N Spare, Hi-Z.
  3 GPIOA3 ASIC_FAIL_N Spare, Hi-Z.
  4 GPIOA4 ASIC_EVENT_N This pin is for asynchronous notification for events that require the host’s attention.
  5 GPIOA5 ASIC_DUALPORTEN_N Spare, Hi-Z
  7 GPIOA7 ASIC_TAP_SEL Spare, Hi-Z
  8 GPIOB0 ASIC_CPU_BOOT_0 Spare, Hi-Z
  9 GPIOB1 ASIC_CPU_BOOT_1 Spare, Hi-Z
  10 GPIOB2 ASIC_M_SCAN_PCAP_SEL Spare, Hi-Z
  11 GPIOB3 ASIC_GPIO_R_0 Spare, Hi-Z
  12 GPIOB4 ASIC_GPIO_R_1 Spare, Hi-Z

Test plan:

• Build code: Pass
• Get GPIO: Pass

Log:

1. Get GPIO list.

• Before modify
  uart:~$ platform gpio list_all
  [2 ] ASIC_PERST1_N : PP | input (I) | 0(0)
  [3 ] ASIC_FAIL_N : PP | input (I) | 0(0)
  [4 ] ASIC_EVENT_N : OD | output(O) | 0(0)
  [5 ] ASIC_DUALPORTEN_N : PP | input (I) | 0(0)
  [7 ] ASIC_TAP_SEL : OD | input (O) | 0(0)
  [8 ] ASIC_CPU_BOOT_0 : PP | input (I) | 0(0)
  [9 ] ASIC_CPU_BOOT_1 : PP | input (I) | 0(0)
  [10 ] ASIC_M_SCAN_PCAP_SEL : PP | input (I) | 0(0)
  [11 ] ASIC_GPIO_R_0 : PP | input (I) | 1(1)
  [12 ] ASIC_GPIO_R_1 : PP | input (I) | 0(0)

• After modify
  uart:~$ platform gpio list_all
  [2 ] ASIC_PERST1_N : OD | output(I) | 0(0)
  [3 ] ASIC_FAIL_N : OD | output(I) | 0(0)
  [4 ] ASIC_EVENT_N : OD | output(I) | 0(0)
  [5 ] ASIC_DUALPORTEN_N : OD | output(I) | 0(0)
  [7 ] ASIC_TAP_SEL : OD | output(I) | 0(0)
  [8 ] ASIC_CPU_BOOT_0 : OD | output(I) | 0(0)
  [9 ] ASIC_CPU_BOOT_1 : OD | output(I) | 0(0)
  [10 ] ASIC_M_SCAN_PCAP_SEL : OD | output(I) | 0(0)
  [11 ] ASIC_GPIO_R_0 : OD | output(I) | 1(1)
  [12 ] ASIC_GPIO_R_1 : OD | output(I) | 0(0)

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