fby3: dl: GPIO oem command#458
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| uint32_t gpio_dir = sys_read32(GPIO_GROUP_REG_ACCESS[gpio_idx / 32] + 0x4); | ||
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| return GETBIT(gpio_dir, gpio_idx % 32); | ||
| } | ||
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| uint8_t get_gpio_interrupt_enable(uint8_t gpio_idx) | ||
| { | ||
| uint32_t gpio_intr_en = sys_read32(GPIO_GROUP_REG_ACCESS[gpio_idx / 32] + 0x8); | ||
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| return GETBIT(gpio_intr_en, gpio_idx % 32); | ||
| } | ||
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| uint8_t get_gpio_interrupt_type(uint8_t gpio_idx) | ||
| { | ||
| uint32_t gpio_intr_type = sys_read32(GPIO_GROUP_REG_ACCESS[gpio_idx / 32] + 0x10); | ||
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| return GETBIT(gpio_intr_type, gpio_idx % 32); | ||
| } | ||
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| uint8_t get_gpio_interrupt_trigger_mode(uint8_t gpio_idx) | ||
| { | ||
| uint8_t trigger_mode = 0; | ||
| uint32_t gpio_intr_dual_edge = sys_read32(GPIO_GROUP_REG_ACCESS[gpio_idx / 32] + 0x14); | ||
| uint32_t gpio_intr_rsing_falling_edge = | ||
| sys_read32(GPIO_GROUP_REG_ACCESS[gpio_idx / 32] + 0xC); | ||
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| if (gpio_intr_dual_edge & BIT(gpio_idx % 32)) { | ||
| trigger_mode = 0x2; //both edge | ||
| } else { | ||
| if (gpio_intr_rsing_falling_edge & BIT(gpio_idx % 32)) { | ||
| trigger_mode = 0x1; //rising edge | ||
| } else { | ||
| trigger_mode = 0x0; //falling edge | ||
| } | ||
| } | ||
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| return trigger_mode; |
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Can we make this a little more generic in case we need to support different boards in the future?
Preferably we wouldn't used hard coded values here and also we would use some of the Zephyr GPIO APIs that might help here.
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https://docs.zephyrproject.org/2.6.0/reference/peripherals/gpio.html
There is no Zephyr GPIO API for getting gpio direction and gpio interrupt information. After discussing with Aspeed, they suggested for maintaining a GPIO status table and get the information from the table. Currently ,we are studying how to implement this feature. Do you have any concern?
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No concern, thank you for looking into this.
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Modify this commit to a function of align ti BIC GPIO number. And the feature of GPIO will be added in the later commit.
Summary: - Align yv3 ti server board gpio number. Test plan: Build code: pass
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Summary: - Remove GPIOG0 interrupt enable due to mis-config before - Disable GPIOO3 in GPIO config because this pin is for LPCRST# function. - Change FM_FORCE_ADR_N to RST_PLTRST_BMC_N on both firmware(CPLD/BIC) and hardware side (Original background: GPIO RST_PLTRST_BMC_N and LPCRST# are same pin on aspeed bic but aspeed bic cannot support dual function at the same time) Dependency: #458 Pull Request resolved: #485 Test Plan: build pass on fby3 dl Reviewed By: peterdelevoryas Differential Revision: D38678804 Pulled By: GoldenBug fbshipit-source-id: 79a5727d98acf091b1a579a1215b98c5615f5fc4
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Summary:
Test plan:
Build code: pass