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1. hackdac_2018_beta hackdac_2018_beta Public

   Forked from hackdac/hackdac_2018_beta

   The SoC used for the beta phase of Hack@DAC 2018.

   SystemVerilog 6

2. opentitan opentitan Public

   Forked from lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   SystemVerilog 1

3. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog