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1. rv_plic rv_plic Public

   Forked from lowRISC/rv_plic

   Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)

   SystemVerilog 1

2. opensbi opensbi Public

   Forked from riscv-software-src/opensbi

   RISC-V Open Source Supervisor Binary Interface

   C

3. sv_exercise sv_exercise Public

   SystemVerilog

4. culsans culsans Public

   Forked from pulp-platform/culsans

   Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

   C 1

5. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   Assembly

6. luca-valente.github.io luca-valente.github.io Public

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