Hi there 👋

I’m an electronics and computer engineering student working on RISC-V processor design and system-level architecture.

• 💻 Designing Out-of-Order RISC-V cores
• 🧠 Interested in hardware/software co-design

My Projects:

• Dual Issue Out Of Order Core: YTS_SIRADISI_Teknofest2024
• C++ Custome Chess: CSE-211-Custom-Chess
• SystemVerilog LIFO: systemverilog-lifo