Skip to content
View niwis's full-sized avatar

Highlights

  • Pro

Block or report niwis

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. openhwgroup/cva6 openhwgroup/cva6 Public

    The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

    Assembly 2.8k 880

  2. riscv-collab/riscv-openocd riscv-collab/riscv-openocd Public

    Fork of OpenOCD that has RISC-V support

    C 507 369

  3. seL4/seL4 seL4/seL4 Public

    The seL4 microkernel

    C 5.3k 736

  4. pulp-platform/cheshire pulp-platform/cheshire Public

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    Verilog 317 94

  5. riscv-admin/timing-fences riscv-admin/timing-fences Public

    Group administration repository for Tech: Microarchitecture Side-Channel Resistant Instruction Spans (uSCR-IS)

    Makefile 3 2