Control and status register code generator toolchain

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…

design and verification of asynchronous circuits

An experimental package manager and development tool for Hardware Description Languages (HDL).

Python Manufacturing Utility or "mupy" is a powerful new digital-twin technology. In it's essence, a new way to think about design, physical hardware, advanced assemblies, innovative technologies, or most generally, system design.

high abstraction synthesis

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates

ChaCha stream cipher modules written in Python, described using Amaranth.

A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.

dosage is a 20bit single cycle RISC cpu based on harvard architecture

SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project

A Scheme Inspired Hardware Description Language

Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.

A Python-based tool for generating Verilog modules with features including customizable state machines, port definitions, and state diagrams using Graphviz. Ideal for FPGA and ASIC design workflows.