About Me

Hello and welcome to my blog!

This is Jzjerry, and welcome to my blog! This blog is a place for me to record my studies & ideas, and sometimes, life as well.

Hong Kong University of Science and Technology (Guangzhou)
- Postgraduate student (Present, Ph.D in Microelectronics) supervised by Prof. Yangdi Lyu
- M.Phil. in Microelectronics (2024.08)
Central South University
- B.S. in Electronic Information Science and Technology (2022.06)

Zijun Jiang and Yangdi Lyu, Microprocessor Design Space Exploration via Space Partitioning and Bayesian Optimization, Design Automation and Test in Europe (DATE), 2024. (Extended Abstract)
Zijun Jiang and Yangdi Lyu, Efficient Microprocessor Design Space Exploration via Space Partitioning, IEEE International Conference on Computer Design (ICCD), 2024. (Short Paper) Code
Zijun Jiang and Yangdi Lyu, MiCo: End-to-End Mixed Precision Neural Network Co-Exploration Framework for Edge AI, International Conference on Computer-Aided Design (ICCAD), 2025. Code
Zijun Jiang and Yangdi Lyu, BNRV: A Lightweight SIMD Extension for Efficient BitNet Inference on RISC-V CPUs, IEEE International Conference on Computer Design (ICCD), 2025. Code

Co-authored

Wujie Zhong, Zijun Jiang and Yangdi Lyu, MACO: A HW-Mapping Co-optimization Framework for DNN Accelerators, Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.
Tong Liu, Zijun Jiang and Yangdi Lyu, CPP-SGS :Cycle-Accurate Power Prediction Framework via SNN and Genetic Signal Selection, Design Automation and Test in Europe (DATE), 2025. (Extended Abstract)
Xiangchen Meng, Yan Tan, Zijun Jiang and Yangdi Lyu, An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren Scheme, Design Automation Conference (DAC), 2025.
Yan Tan, Xiangchen Meng, Zijun Jiang and Yangdi Lyu, AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code, Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.

To Be Continued…

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