Ayush Singhal

Developed location and depth based static timing analysis tool (LOCV/AOCV) considering local variations and common path pessimism removal (C++ - STL). Studied the impact of LOCV, OCV and CPPR vs NON-CPPR.

Minor Project: Developed a robot which can be controlled by computer or laptop.

Proposed an optimized design of Adaptive headlight offering driver better visibility and submitted it in International Journal of Computers and Technology.

Developed an off road vehicle for National Level Event with new innovations and got first prize for the most cost effective off road vehicle worth Rs. 1,00,000. In this project, I worked as Head designer and design three new innovation based on control system and embedded system.

Advanced Scientific And Technical Conference: Presented a research paper on Artificial Brain in a
conference organized by RCMA and Defense Research and Development Organization in year (2010-11).

Designed an improved prototype of Hybrid solar energy and submitted in Chandigarh Science Conference 2012. We suggested an interface between natural light and artificial light which results in 35% reduction in electricity consumption.

Developed a concept where we generated a small voltage using magnetic energy stored in pyramid and presented as a project in Chandigarh Science conference 2012.

Completed the RTL implementation of AMBA 2.0 AHB protocol for the slave and verified the functionality.
Used Synopsis VCS for simulation, Design Vision tool for synthesis and Synopsys - IC Compiler for floorplanning and automated routing.
Used different optimization techniques to synthesis the design and based on the results (slack, area & power) obtained, an optimal techniques was decided for the final implementation.
ATPG was performed for the design.
Generated the Layout for the… Show more

Completed the RTL implementation of AMBA 2.0 AHB protocol for the slave and verified the functionality.
Used Synopsis VCS for simulation, Design Vision tool for synthesis and Synopsys - IC Compiler for floorplanning and automated routing.
Used different optimization techniques to synthesis the design and based on the results (slack, area & power) obtained, an optimal techniques was decided for the final implementation.
ATPG was performed for the design.
Generated the Layout for the design using IC-compiler. Show less

Custom design of 128-kbit SRAM (Layout and Schematic) with leakage reduction schemes (power gating) and write assist circuits in 45 nm Technology. Worst case (Read after Write for the critical path) frequency of 1.1 GHz was achieved for a VDD of 1.1V @ 80 Deg C.

Schematic for the critical path was designed by including parasitic resistance and capacitance so that results matches closely with the post-layout results.

Exhaustive characterization of Static Noise Margins was done… Show more

Custom design of 128-kbit SRAM (Layout and Schematic) with leakage reduction schemes (power gating) and write assist circuits in 45 nm Technology. Worst case (Read after Write for the critical path) frequency of 1.1 GHz was achieved for a VDD of 1.1V @ 80 Deg C.

Schematic for the critical path was designed by including parasitic resistance and capacitance so that results matches closely with the post-layout results.

Exhaustive characterization of Static Noise Margins was done against process variations through Monte-Carlo simulations to optimize the design of SRAM bit-cell.

SRAM also supports sleep mode which results in leakage power reduction to 64.58% when the SRAM sub-array is not in use. This achieved by clamping the ground voltage at 0.3V during sleep mode. Whereas SRAM wakes up in 10ns and with peak current of 4.2mA.

Studied the retention time for the SRAM bit cell and implemented the interleaved transient voltage collapse write assist (TVC-WA) to speed up the write process. The SRAM array's VDD node was dropped to 200mV (for 158 ps) while writing the data, without affecting the pseudo read operation. With TVC-bias circuitry to increase the yield.

Quadrant Style Architecture was used for the layout (with row and column decoders and timing circuitry at the central area, to minimize the delay and skew due to RC).

Post layout Physical Verification (LVS/DRC check) and parasitic extraction was done using Mentor Graphics Calibre. Post layout Corner Simulation of the critical path was done in HSPICE to ensure correct operations. Post Layout frequency was 1.1 GHz @ 80Deg C. With area efficiency of 82.12%.

SKILL Scripting was used to generate 128kB SRAM core array, column circuit and row decoder array.






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VLSI Desgin 1 (Graduate Course) Project under Prof. Chris Kim.
-- Area = 139 sq microns, Technology: 45nm , 1.1V
-- 962MHz worst case Frequency at 1.1V

-- Designed the schematic & layout of 16bit - adder using Cadence Virtuoso, simulation was carried out using FreePDK 45 nm technology.
-- Modeled the circuit and finding the transient conditions using HSPICE
-- Analyzed the values and the waveforms using Synopsys Cosmoscope.
-- DRC and LVS check was performed for the… Show more

VLSI Desgin 1 (Graduate Course) Project under Prof. Chris Kim.
-- Area = 139 sq microns, Technology: 45nm , 1.1V
-- 962MHz worst case Frequency at 1.1V

-- Designed the schematic & layout of 16bit - adder using Cadence Virtuoso, simulation was carried out using FreePDK 45 nm technology.
-- Modeled the circuit and finding the transient conditions using HSPICE
-- Analyzed the values and the waveforms using Synopsys Cosmoscope.
-- DRC and LVS check was performed for the layout of the circuits and its verification using Mentor Graphics.
-- Grid based standard cell layout technique was used to make Layout. Show less

VLSI Design Automation I (Graduate Course) Project under Prof. Sachin S. Sapatnekar.
Implemented a circuit partitioning in C++/STL using Simulated Annealing algorithm in order to create a balanced partition with minimized cut size. Code can handle upto 500,000 gates/blocks.For a large sized netlist, there was reduction in cut size from 5241 to 429 with in optimal time.

VLSI Design Automation I (Graduate Course) Project under Prof. Sachin S. Sapatnekar.
Wrote a code in C++/STL which performs static time analysis for a netlist.

Worked as a team captain and developed a semi-automatic vehicle prototype (1:1 model) using software Matlab, LabVIEW and its associated DAQ card and presented the research paper in a National level event organised by National Instruments and secured first prize worth Rs.50000.