Questions tagged [fpga]
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing.
21 questions
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Button Debounce in Verilog
I'm learning FPGA development, and this is my first Verilog module - a button bouncer using a state machine. The code works as I expected it to be, but I would like some feedback on the code itself ...
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3
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Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog
Question
How can I improve my Verilog code?
Context
Flash Read ID Operation
This project is an implimentation of the Read Manufacturer and Device ID (9Fh) operation ...
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3
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1
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SPI prototype in Verilog: areas for code improvement
I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...
- 133
3
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1
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Detect when X-axis inputs and Y-axis inputs go high
I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
4
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1
answer
162
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Design and stimulus for a simple Mealy finite state machine
I am trying to code a state machine for the given state diagram:
I
...
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1
vote
1
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134
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Clock frequency meter module
The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
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5
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LED matrix controller - Verilog
I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...
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1
vote
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fixed pseudo-random binary sequence (prbs)
On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
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4
votes
1
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Heart beat RTL module
Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
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2
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1
answer
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pseudo-random binary sequence (prbs)
Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
- 453
3
votes
1
answer
2k
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Carry Lookahead Adder - SystemVerilog
I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...
- 193
2
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0
answers
421
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a simple interrupt polling program due to AXI DMA IP
The program transfers a data array from a Zynq-7000 PS DDR to a BRAM IP (block RAM) memory in a PL part of a FPGA due to a PL AXI DMA IP. Inferring a xilinx axi dma driver (not scatter-gather mode), ...
- 453
6
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1
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841
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VGA sync generator for 640x480@60Hz
I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...
- 261
7
votes
1
answer
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Signal output on Raspberry Pi that acts as input for FPGA
Problem
I'm writing a verilog program that does the trapezoidal integration method (where a review is also welcome, wink wink). But turns out you need input for these kind of things, so in the overly ...
- 441
6
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2
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Verilog implementation of trapezoidal integration method
Any and all comments are welcome in this review.
##Problem
I've been doing a lot with numerical integration methods recently and have mostly been programming in Python. But, speedups and FPGAs are ...
- 441