Questions tagged [hdl]
HDL stands for hardware description language. The most common examples are VHDL and verilog.
19 questions
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RISCV ALU Implementation in SystemVerilog
This will be first of many things I will submit during my journey of self (re)learning CPU design.
I have ALU implementation for RiscV base instruction. I am not fully sure what I am looking
for, but ...
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3
votes
1
answer
120
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SPI prototype in Verilog: areas for code improvement
I'm working on an SPI in Verilog. I will post what I came up with here. This is an educational project compiled according to the general principle from Wikipedia. There is only one mode - exchange ...
- 133
3
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1
answer
103
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Detect when X-axis inputs and Y-axis inputs go high
I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
4
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1
answer
162
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Design and stimulus for a simple Mealy finite state machine
I am trying to code a state machine for the given state diagram:
I
...
- 43
2
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1
answer
319
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SystemVerilog implementation of an N-bit prefix adder logic design
I want some feedback about my code (anything is welcome). It is working, but it feels like a clumsy implementation. Because I am self-learning from a book without an answers section, it becomes ...
5
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1
answer
742
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LED matrix controller - Verilog
I'm an ECE student. My experience in Verilog and FPGAs is mainly from my digital logic design class. To practice Verilog, I decided to implement a controller for Adafruit LED matrices. It interfaces ...
- 143
2
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1
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2k
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pseudo-random binary sequence (prbs)
Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
- 453
3
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1
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Carry Lookahead Adder - SystemVerilog
I have been learning SystemVerilog before I go back to school and decided to try and implement a Carry Lookahead Adder. As far as I can tell, it works correctly though I haven't tested extensively, ...
- 193
5
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2
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Generate a sine wave
This ip core simply generates a sine wave according a .mem file. It is required to specify rom depth equal to number of the sine points, the init file and the data size contained in the file. The ...
- 453
3
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1
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128
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Pulse-width modulation module
Module for generating a PWM signal. The req_value_i input gets a duration value of the signal. Furthermore, the module can be stopped by deassertion of the enable_i input.
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- 453
3
votes
1
answer
644
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Parameterized Verilog shift register code
I am a beginner in FPGAs, and I am studying Verilog HDL. Could you please check the quality of my code (a shift register)? Any comments are welcome.
The shift register serializes parallel from ...
- 453
6
votes
1
answer
841
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VGA sync generator for 640x480@60Hz
I wrote my first module in Verilog. The purpose is to maintain two counters and emit signals corresponding to VGA's HSync and VSync, as well as HBlank and VBlank pulses to be used by a video ...
- 261
6
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2
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2k
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Simple SystemVerilog AXI controller
I have a more long-term project I'm using to learn FPGA/HDL, and this is first sub-component of it used for testing. I'm targeting Zynq device.
I'd like to create a component which creates an image. ...
- 161
8
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2
answers
8k
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8-bit ALU in Verilog
I'm an EE student who's taken a a couple digital logic/design courses, but they were focused on schematic representation, so I'm teaching myself Verilog to implement what I've learned.
For a basic &...
3
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2
answers
8k
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