How to generate true DDR output with OSERDES2 in Spartan-6 without an external high-speed clock (BUFIO2 not possible)?

I’m working on a Spartan-6 design where I need to generate DDR output data using OSERDES2, but I don’t have an external high-speed clock available. Here’s my setup and the challenge I’m running into:

Design goal

• Source clock: 40 MHz
• Use a PLL_BASE to generate:
  • 320 MHz (data clock for IOCLK)
  • 80 MHz (frame clock for CLKDIV)
• The OSERDES2 should serialize 8 bits of parallel data (80 MHz) into DDR output at 320 MHz, producing 640 Mb/s at the pin.

What I tried

• I use the PLL to generate the fast/slow clocks.
• I feed the PLL outputs into BUFPLL, since BUFIO2 requires an external high-speed clock and can’t be driven by a PLL output.
• BUFPLL generates:
  • IOCLK (320 MHz) → OSERDES2.CLK0
  • SERDESSTROBE → OSERDES2.IOCE
  • CLKDIV (80 MHz) → via BUFG to OSERDES2.CLKDIV

OSERDES2 is configured as:

.DATA_WIDTH(8)
.CLK0(IOCLK)
.CLK1(1'b0)
.CLKDIV(CLKDIV)
.IOCE(SERDESSTROBE)
.OCE(1'b1)
.SERDES_MODE("MASTER" / "SLAVE") 

MASTER + SLAVE are cascaded for 8:1 DDR serialization.

The problem

In simulation, the output (OQ) acts like SDR, not DDR. According to UG381/UG382, BUFPLL is typically used for SDR, while BUFIO2 (which I can’t use) is for DDR clocking from an external source. But I don’t have a high-speed input clock — all I have is the 40 MHz reference and the PLL-generated 320 MHz clock. The documentation says CLK1 is needed for DDR operation, but if I tie it low, I only see SDR. If I don’t have a true differential or 2-phase 320 MHz source, how do I drive CLK1?

My questions

1. How can we use OSERDES2 to generate true DDR data when the high-speed clock comes from a PLL, not an external pin?
2. If BUFIO2 requires an external input clock, what is the correct way to create the equivalent internal DDR IO clocking?
3. Does BUFPLL actually support DDR operation (both edges), or is it limited to SDR output timing as UG381 seems to imply?
4. How should CLK1 of OSERDES2 be driven in this case — or is it truly optional when using BUFPLL?
5. Has anyone successfully implemented a DDR OSERDES2 transmitter on Spartan-6 without an external high-speed clock (using only PLL/BUFPLL)?