Electronics & Communication Engineering (VLSI) Graduate | Semiconductor Enthusiast
I am an Electronics and Communication Engineering (VLSI) graduate from VIT-AP University with a strong interest in ASIC Physical Design, Digital VLSI, and Semiconductor Technology.
I am currently working as an ASIC Physical Design Intern at Synopsys, where I am building practical knowledge of ASIC implementation, physical design, timing analysis, and RTL-to-GDS flow.
I have hands-on experience through internships and academic projects involving Digital VLSI, FPGA implementation, Verilog, Quantum Key Distribution, Cadence tools, and robotics.
- ASIC / VLSI: Physical Design, RTL-to-GDS, Static Timing Analysis, Digital VLSI
- HDLs: Verilog, SystemVerilog
- EDA Tools: Cadence Virtuoso, Genus, Innovus, Tempus, Spectre, Xilinx Vivado
- Physical Design: Synthesis, Floorplanning, Placement, CTS, Routing, Timing Analysis
- Physical Verification: DRC, LVS, PEX, Post-Layout Simulation
- Programming: Python, C, Java
- Hardware: FPGA, Digital Logic Design, Circuit Analysis
- Working in the area of ASIC Physical Design.
- Learning and working with RTL-to-GDS implementation flows.
- Developing practical understanding of floorplanning, placement, CTS, routing, timing analysis, and physical verification.
- Exploring industry-standard EDA tools and semiconductor design methodologies.
Digital VLSI Circuit Design and FPGA Implementation of QKD Post-Processing
- Designed Verilog-based hardware blocks for Quantum Key Distribution (QKD) post-processing.
- Implemented Sifting and Privacy Amplification hardware blocks.
- Developed a radix-16 Cooley-Tukey NTT architecture.
- Worked with modular arithmetic, hashing, memory blocks, FSMs and FPGA implementation.
- Verified the design using Verilog testbenches and waveform analysis.
3-DOF Robotic Manipulator
- Developed a 3-DOF robotic manipulator using ROS 2, MoveIt and Gazebo.
- Worked with Python, URDF and OpenCV.
- Implemented trajectory planning and robotic control.
- Designed a 4KB SRAM using a Noble Schmitt Trigger-based 12T SRAM bit cell.
- Implemented schematic and layout using Cadence Virtuoso.
- Worked with DRC, LVS, PEX and post-layout simulation.
- Designed and analyzed memory read/write operations and peripheral circuitry.
- Worked with the PicoRV32 RISC-V processor.
- Explored RTL synthesis and ASIC implementation flow using Sky130 PDK.
- Worked with Cadence Genus and Innovus.
- Studied synthesis, timing constraints, placement, routing and timing analysis.
- ASIC Physical Design
- Static Timing Analysis (STA)
- Timing Closure
- Clock Tree Synthesis (CTS)
- Placement & Routing
- Physical Verification
- RTL-to-GDS Flow
- Advanced VLSI Design Methodologies
Verilog SystemVerilog Python C Java
Cadence Virtuoso Genus Innovus Tempus Spectre Vivado
RTL Design Synthesis Floorplanning Placement CTS Routing STA DRC LVS PEX
Git Linux FPGA ROS 2
- ASIC / VLSI Design Projects
- RTL Design and Verification
- FPGA Development
- Digital Design
- RISC-V Projects
- Semiconductor / EDA Open Source Projects
- 📧 Email: sourabhtyagi750@gmail.com
- 💼 LinkedIn: Sourabh Tyagi
