[Nexthop][NPI] "asic_config_v3" - Add minipack3bta platform and its variants

[marif-nexthop]

Pre-submission checklist

• I've ran the linters locally and fixed lint errors related to the files I modified in this PR. You can install the linters by running pip install -r requirements-dev.txt && pre-commit install
• pre-commit run

Summary

Implements asic_config_v3 design.

In this PR, add platform configuration for the internal variant of minipack3bta platform.

After this commit the asic_config_v3 generator produces the following extra output file

• fboss/lib/asic_config_v3/generated_asic_configs/minipack3bta_internal.yml

Test Plan

The generated output is compared against the asic_config_v2 synced config:

$ diff fboss/lib/asic_config_v3/generated_asic_configs/minipack3bta_internal.yml fboss/lib/asic_config_v2/synced_asic_configs/minipack3bta.yml

The remaining differences are in the platform_mapping_v2-derived port-mapping data (the PC_PHYS_PORT_ID map and the PORT blocks). minipack3bta wires 4 of 8 lanes per port and uses a linear-stride layout, so asic_config_v3 emits the correct stride-4 port ranges, while the asic_config_v2 synced config is stale and still carries the older stride-2 port map.
These differences are expected.