Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.
Convolutional accelerator kernel, target ASIC & FPGA
hardware design of universal NPU(CNN accelerator) for various convolution neural network
A FPGA Based CNN accelerator, following Google's TPU V1.
A DNN Accelerator implemented with RTL.
Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植
2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition
Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
Small-scale FPGA-based Neural Processing Unit (CNN Accelerator) with INT8 systolic array matrix multiplication in Verilog.
Modified version of the "Explore the energy-efficient dataflow scheduling for neural networks. "
SystemVerilog FPGA acceleration of LeNet-5 CNN for Fashion-MNIST classification, powered by a 5x5 2D Torus Systolic Array with bit-exact Python simulator, and out-of-context Vivado synthesis benchmarks.
Parameterized NxN systolic-array NPU for signed matrix multiplication, implemented in SystemVerilog RTL and verified using UVM, SVA, directed testing, formal verification, functional coverage, and multi-configuration regression.
Synthesizable INT8 CNN accelerator with bit-exact Python/RTL verification and a replaceable MAC interface.
CNN accelerator datapath components
Parameterizable output-stationary INT8 systolic MAC array in Verilog, extended into a weight-stationary 3-layer CNN accelerator (Conv1->Conv2->FC) with interlayer requantization. 20/20 samples bit-exact end-to-end vs a Python golden model; 1,900-case model sweep plus a 206-case constrained-random SV suite. CI on every push.
Verilog implementation of a CNN-style image processing pipeline with convolution, activation, pooling, and RTL-based verification.
Custom FPGA hardware accelerators for image processing (5x5 Convolution & Sobel Edge Detection) on the Zynq-7000 SoC using Verilog, AXI4-Stream, and PYNQ.
A CNN processor that takes layers of CNN as input instruction and performs the respective operation.
Runs all 22 layers of YOLOv2 on a single Artix-7 FPGA
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