tag: verification

Transforming DRC Closure At Advanced Nodes
By James Paris - 30 Apr, 2026 - Comments: 0

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

Assuring Comprehensive Security Coverage In Hardware Design
By Arteris - 29 Apr, 2026 - Comments: 0

Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs. By adopting a systematic framework and measuring coverage throughout the pre-silicon development cycle, you can proactively identify vulnerabilities and strengthen your hardware’s resilience. Downl... » read more

Building An AI Chip: Silicon Design And Advanced Packaging
By Synopsys - 29 Apr, 2026 - Comments: 0

AI has become a key driver for the semiconductor industry as it is applied to ever more aspects of daily life. Many startups and established vendors are designing AI chips to accelerate algorithms and yield the best results. AI designs are large and complex, requiring advanced process nodes and putting stress on every step of the development process. Multi-die, or chiplet-based, design is becom... » read more

Emulation-based SoC Security Verification (U. of Florida)
By Technical Paper Link - 17 Apr, 2026 - Comments: 0

A new technical paper, "Emulation-based System-on-Chip Security Verification: Challenges and Opportunities," was published by researchers at University of Florida. Abstract "Increasing system-on-chip (SoC) heterogeneity, deep hardware/software integration, and the proliferation of third-party intellectual property (IP) have brought security validation to the forefront of semiconductor desig... » read more

Shift Verification Left: AI Tools For Faster, Smarter Chip Design
By Hamid Shojaei - 26 Mar, 2026 - Comments: 0

Verification activities can consume up to 70% of an overall chip project's effort, underscoring the central challenge that verification poses in today's semiconductor development (Cadence SoC Verification report). The most time-consuming activities, debugging and coverage closure, require significant coordination between design and verification teams and largely dictate overall time-to-ma... » read more

AI Won’t Kill Verification IP, But It Will Redefine It
By Ann Mutschler - 26 Mar, 2026 - Comments: 0

Key Takeaways AI will enhance, not replace, verification IP by automating test generation and debug. Verification IP’s core value will increasingly lie in trust, accountability, and system-level realism, especially as designs become more complex, multi-die, and security-sensitive. AI shifts verification bottlenecks from execution to specification quality, raising expectations for c... » read more

The Future of Semiconductors: Engineering in the Convergence era
By Siemens EDA - 09 Mar, 2026 - Comments: 0

The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade. Moore’... » read more

Across The Vast Reaches Of The 3D Stack: Mastering ESD Verification In Advanced Semiconductor Design
By Keerthana Chelur Hithesh - 05 Mar, 2026 - Comments: 0

Introduction: The epic challenge In the vast reaches of the semiconductor cosmos, a silent menace lurks—one that can obliterate years of design work in a fraction of a nanosecond. Electrostatic discharge (ESD) verification stands as the guardian against this invisible threat, a critical discipline that separates the triumphant chip designs from the smoldering wreckage of failed silicon dream... » read more

Limiting AI/ML Tools To Ensure Physical AI Safety, Security
By Liz Allan - 05 Mar, 2026 - Comments: 0

Key Takeaways: AI-based tools can help monitor physical AI systems and LLMs, but human oversight is still needed to avoid false positives, bias, and other anomalies. For autonomous vehicles and robots, edge case scenarios and understanding human values are weak points, especially as moral and social values change over time. AI tools are growing and becoming increasingly helpful for c... » read more

System-level Reliability Verification for 2.5D/3D ICs Using Innovator3D IC and Calibre 3DPERC
By Siemens EDA - 04 Mar, 2026 - Comments: 0

The increasing demand for higher performance, lower power, and greater functionality in smaller packages has driven the rapid adoption of 2.5D and 3D Integrated Circuits (ICs). However, the inherent complexity of these multi-die architectures presents significant reliability verification challenges that traditional 2D flows cannot adequately address, particularly concerning electrostatic discha... » read more

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