Mustafa Altintas

NVIDIA picks Micron Technology for massive SOCAMM rollout 🤩 #Nvidia is preparing to enter a new phase in the memory market by planning to deploy between 600,000 and 800,000 SOCAMM modules in 2025. This initiative positions SOCAMM as a potential successor to high-bandwidth memory (#HBM). Although the initial deployment volumes are relatively modest compared to HBM, industry analysts suggest the move could trigger a wider transformation in the #memory and substrate sectors. According to reports from ET News and Wccftech, Nvidia has confirmed its intent to integrate SOCAMM into its next-generation #AI products, sharing projected order quantities with key #memory and substrate suppliers. The company's upcoming GB300 "Blackwell" platform will be among the first to adopt SOCAMM, alongside the AI PC Digits, unveiled during Nvidia's GTC 2025 conference in May. Nvidia initially tapped Samsung Electronics, SK hynix, and Micron Technology to co-develop SOCAMM. However, #Micron has emerged as the first memory maker to receive approval for volume production, outpacing its South Korean rivals in the race to support Nvidia's latest architectures. Thanks again to Amy Fan , Sherri Wang and DIGITIMES Asia for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eAjnXYQu #semiconductorindustry #semiconductors #technology #tech #innovation #usa #taiwan #geopolitics #datecenter #dram #ai #server #chip #ic #aiot

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*** New To Chiplets World: What I’d Focus On *** As a new engineer entering the world of chiplets, the learning curve is steep, but there are three areas I’d focus on first: 1.Understanding the interconnects. The core of chiplet-based SoCs is the inter-chiplet communication.Whether it’s UCIe, BoW, EMIB, or any other protocol, understanding how data moves between chips is crucial. If you don’t get how chiplets communicate, you won’t understand how your design will work in a multi-die system. 2.System-level thinking. Chiplet designs aren’t about optimizing individual chips—they’re about creating a coherent system. As a new engineer, it’s essential to look beyond the chiplet’s boundary and think about how your piece fits into the larger architecture. Understanding power, thermal, & communication interactions is key. 3.Verification from the start. The hardest issues with chiplets often surface at integration. Focus on building verification strategies early—both at the individual chipletlevel and in the full-chip system. A deep understanding of how chiplets interact will be your biggest asset. If you were starting fresh in the chiplet world, what would you prioritize?

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RF Basics: Down-Conversion Mixer A down-conversion mixer is a crucial component in radio frequency (RF) systems, especially in receivers. Its primary function is to lower the frequency of an incoming RF signal to an intermediate frequency (IF) or baseband frequency, making it easier to process and amplify. Here's how a down-conversion mixer works and why it's important: 1. The mixing process: A down-conversion mixer has three ports: an RF input, a local oscillator (LO) input, and an IF output. The RF port receives the high-frequency signal that needs to be down-converted. The LO port receives a steady, high-frequency signal generated by a local oscillator. The mixer combines these two signals using a nonlinear element (like diodes or transistors). This mixing process creates new frequencies at the output, including the sum (RF + LO) and difference (RF - LO) of the input frequencies. 2. Down-conversion to IF: In a down-conversion mixer, the desired output is the difference frequency (f_RF - f_LO) which is at a lower frequency than the input RF signal. This lower frequency is known as the intermediate frequency (IF). This process allows for better filtering of unwanted signals and noise at the lower frequency range, ultimately improving the signal-to-noise ratio. 3. Applications: Down-conversion mixers are widely used in receivers, particularly in superheterodyne receivers, which are common in radios, televisions, and cellular base stations. They are also essential in radar systems, satellite communications, and other applications requiring frequency translation for signal processing. 4. Importance in RF systems: Efficient signal handling: Down-conversion enables systems to process high-frequency signals more effectively by shifting them to a more manageable frequency band. Improved selectivity and sensitivity: Filtering is more effective at lower frequencies, allowing the receiver to better isolate the desired signal from interference and noise. Enhanced system performance: By reducing the frequency and facilitating filtering, down-conversion mixers contribute to overall system performance and efficiency. In essence, down-conversion mixers are key to making high-frequency signals accessible and manageable for various RF applications, contributing significantly to the performance of modern communication and electronic systems. 🙏🙏🙏🙏🙏

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🔥 Multi-Core Design: The Hidden Battle of Power and Performance   🧠   Why Multi-Core?     Single-core GHz race hit a wall.   Heat and power skyrocketed.   Multi-core scaled performance without chasing GHz.    ⚡   But Here’s the Catch     More cores = more complexity.   Dynamic Voltage and Frequency Scaling (DVFS) became critical.   Why? Because workloads vary.   AI inference needs bursts. Idle cores need power gating.    🔍   DVFS Challenges      Multiple voltage domains    Per-core frequency tuning    Timing closure across dynamic states    IR-drop risk during voltage transitions 🏗   Power Delivery Challenges      Dense power grids for 100+ cores    Droop control during DVFS switching    Package-level integrity for AI accelerators    EM reliability under dynamic loads 🔥   Without mastering DVFS and power delivery, multi-core efficiency collapses.     AI chips demand   performance per watt  , not GHz bragging rights. 💬   Your Turn     What’s harder in sub-3nm era?   DVFS complexity or power integrity?   Comment below 👇 #VLSI #PhysicalDesign #MultiCore #DVFS #PowerDelivery #AIChips #Semiconductors #EDA #SoC

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Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent

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HBM (HBMIO) and DDR are both DRAM technologies, but they are optimized for very different system goals. The differences span physical stacking, I/O interface, bandwidth, power, latency, packaging, and use cases. 1. Physical Stack & Packaging HBM Memory Stack • 3D stacked DRAM dies (4-Hi, 8-Hi, 12-Hi) • Dies connected using TSVs (Through-Silicon Vias) • Mounted on a silicon interposer next to the SoC • SoC ↔ HBM distance: millimeters DDR Memory Stack • 2D discrete DRAM chips • No TSV stacking (except internal DRAM techniques) • Placed on DIMMs or soldered on PCB • SoC ↔ DRAM distance: centimeters 2. I/O Architecture (Most Important Difference) HBMIO Interface • Extremely wide bus • 1024-bit per HBM stack (HBM2/2E) • Split into 8 independent channels • Low frequency • ~1–3.2 Gbps per pin • Massive parallelism DDR Interface • Narrow bus • 64-bit per channel (+ ECC) • Very high frequency • DDR5: 4.8–8.8 Gbps per pin • Few channels (2–8 typical) 3 . Bandwidth Comparison Bandwidth per Stack / Channel Memory Type-Bandwidth 1. HBM2-256 GB/s per stack 2. HBM2E-410 GB/s per stack 3. HBM3-800+ GB/s per stack 4. DDR5 (1 channel)-38–70 GB/s 4. Power Efficiency HBM achieves: • Lower I/O power • Better GB/s per watt 5. Quick Summary Table

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It’s exciting to see chiplets go from concept to reality and even more exciting to see Arm playing such a key role in making it happen. Arm's ecosystem is leading the way: Amazon Web Services (AWS), Ampere, and NVIDIA are all building modular, disaggregated systems that unlock performance, efficiency, and flexibility. Proud to be part of the team shaping the future of compute. Check out this great read by Austin L.: https://okt.to/R2qch3

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We’ve now seen the full spectrum of operator optimization, from kernels that are implemented purely in C, to those that leverage hardware instructions provided in architecture extensions, and finally to those that offload inference to a wholly separate processor. In future posts, we’ll explore how operators are encoded in .tflite files, and how the runtime ultimately invokes the underlying kernels. https://lnkd.in/e5xVMRHU

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Snapdragon 8 Elite Gen 5 for Galaxy builds on the decades-long strategic partnerships between Qualcomm and Samsung Electronics as it begins powering the Galaxy S26 series. This generation raises performance and supports more advanced agentic AI on the device for demanding mobile workloads. Learn more here:  https://lnkd.in/daVTkxPU

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