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14K followers
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Mustafa Altintas shared thisTech giants are rushing to develop their own chips — here’s whyTech giants are rushing to develop their own chips — here’s why
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Mustafa Altintas shared thisMustafa Altintas shared thisVideo around my new anamorphic installation of Mustafa Kemal Atatürk. I created it from the 584 items, which are touching his life and legacy. Installation is like presidential office, where all the items move into his portrait. . Installation is on display now on Izmir Marble Fair at Hall B, stand B196 until saturday evening. Come to see it in real! . @temmermarble . #Ataturk #legacy #today
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Mustafa Altintas shared thisThe node chart in the Semiwiki post is quite instructive. 10 years ago, there was almost a religious trust in the tick-tock cadence: process tick in odd years, and u-arch tock in even years. The magic cadence may have been broken due to lack of technical leadership or the proverbial butterfly flapping its wings but considering that Intel is a business (not a research outfit) the complacency that started putting MBAs at the helm is probably because of the 2-decade x86 run that conquered desktop, laptop and servers, all the while ignoring mobile. And mobile at the end helped bring down foundry supremacy. Even for 14nm, Intel was hoping that its own mobile chips could help fill 14nm capacity and recoup the huge foundry investment. In this sense, the move to sign up QCOM is about 10 years late. And one can learn from making chips for others: Samsung made early iPhone chips for Apple and earned/learned a lot whereas Intel was thinking mobile meant laptops at that time and looked down on phone app processors and baseband processors.Mustafa Altintas shared thisWhy a GF acquisition absolutely makes sense for Intel. https://lnkd.in/dXVef7h #intel #globalfoundries
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Mustafa Altintas shared thisBioNTech founders receive one of Germany's highest honors – DW – 02/26/2021BioNTech founders receive one of Germany's highest honors – DW – 02/26/2021
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Mustafa Altintas shared thisWhy is there a chip shortage for computers and cars?Why is there a chip shortage for computers and cars?
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Mustafa Altintas shared this"The value of my stake doesn't interest me," [Ugur Sahin] told German news website Wirtschaftswoche. "We wanted to build up a firm similar to biotech giants like Amgen or Genentech. We want to create long-term value. That's what interests me."Coronavirus: Turkish Germans raise new Covid vaccine hopesCoronavirus: Turkish Germans raise new Covid vaccine hopes
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Mustafa Altintas shared thisWe are hiring senior ASIC/SoC engineers (at least 10 yrs of solid semiconductor industry experience) to work on low-power wireless System-on-Chip products targeting the wireless connectivity market and beyond. A wide range of skills (microarchitecture, RTL design/verification, chip integration, DFT, MBIST, synthesis, UPF, STA, LEC as welll as power estimation and FPGA emulation) is appreciated. Domain experience in Bluetooth, IOT, Audio and similar segments is welcome but not mandatory. Come and join a growing design team on exciting projects. Please apply via LinkedIn by clicking the link below. #hiring #asicdesign #socdesign #wireless #lowpower #goodix
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Mustafa Altintas liked thisBehzad Razavi… many of us grew up learning from his books—Design of Analog Integrated Circuits and RF Microelectronics. It was a real privilege to see him today at ITU Green Building and briefly express my respect to someone who has shaped how we understand analog design. Moments like this remind you how much impact great educators can have across generations. The auditorium was full of next generation Razavis. Thanks to folks at İTÜ IEEE Student Branch and ITU VLSI Laboratories for the organization.. (Side note: campus accessibility—like parking policies—really shapes the visitor experience more than we think. Charging a researcher or even students visiting for a talk $10 for 3 hours parking is not acceptable, as I do not recall paying a penny for visiting a research talk at ODTU.) Hasan Mandal Abdül Halim Zaim
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Mustafa Altintas liked thisMustafa Altintas liked thisHürmüz Krizi'yle felaket senaryoları yeniden dolaşıma girdi. Eski bir sektör yöneticisi olarak düşüncelerimi paylaşıyorum: - Öncelikle petrol-doğalgaz ayrımı şart. Petrolden başlayalım: Petrol, hem tedarik kaynakları hem de lojistik rotaları açısından muazzam çeşitlendirilmiş, dünyanın en likit ve en çok trade edilen emtia piyasasıdır. - Dünyada artık petrol kıtlığı yok, tam tersine petrol bolluğu var. Neden? 1) ABD’de bulunan fracking teknolojisi sayesinde shale oil üretimi müthiş arttı. Bugün dünyanın en büyük üreticisi artık S.Arabistan değil, ABD (tabii ABD aynı zamanda en büyük tüketici olduğu için ihracatta 3., en büyük ihracatçı hala Suudiler). 2) Sondaj teknolojileri sayesinde artık mevcut kuyulardan çok daha fazla üretim yapılabiliyor. 3) Petrol talebi artışı yavaşladı. Bir yandan nüfus/sanayi büyümesiyle talep artıyor ama iklim politikaları sayesinde petrole talep düşüyor. Bu +/- birbirini dengelediği için de talep artık stabil seyrediyor (1990 66 milyon varil/gün → 2010 87m → 2019 Covid öncesi 100m → 2025 103m). - Petrolde sorun kıtlık değil, fiyat. Yani bugün hem sizin hem de ülkenizin bütçesi sağlam ise, istasyona gidip de benzin bulamama ihtimaliniz yok. Asıl kriz a) hane halkının kendi aylık bütçesini b) hükümetlerin de cari açığı ve enflasyonu yönetebilme kapasitesinde. - Gelelim doğalgaza: Hürmüz’ün asıl etkisi petrolden ziyade doğalgazda. Neden? Çünkü doğalgaz üretimi, petrole nazaran çok daha grift bir yatırım. Bugün Afrika’nın ücra köyündeki petrolü bile tankerle komşu ülkeye satabilirsiniz, ama gazın pazara erişimi hiç ama hiç kolay değildir. Hem keşif+üretim aşaması daha maliyetlidir hem de kuyudan nihai tüketiciye ulaştırılması için muazzam bir iletim (midstream) yatırımı şarttır. Ya milyarlarca dolar yatırımla yüzlerce kilometre boru hattı inşa ederek komşu ülkelere karadan ulaştırırsınız (ör. Rusya – Türkiye arasındaki Mavi Akım) ya da yine milyarlarca dolar yatırımla LNG terminalleri (üretici ülkede sıvılaştırma, alıcı ülkede gazlaştırma) inşa ederek gemilerle taşırsınız (ör. ABD'deki Sabine Pass ve ülkemizdeki Marmara Ereğlisi). - Yani gaz, petrol gibi likit bir emtia değildir. Daha ortada keşif bile yokken, tüm tedarik zincirini uçtan uca planlamanız gereken çok katmanlı bir değer zinciridir. Bu yüzden de petrol piyasası büyük oranda spot işlemlere dayanırken, gaz piyasası uzun vadeli al ya da öde (take-or-pay) kontratlarına dayanır (küresel LNG ticareti kabaca %70 1+ yıl kontratlar vs %30 spot). - Hürmüz Krizi nedeniyle hem dünyanın en büyük gaz sahası (South Pars) ve dünyanın en büyük LNG üretim kompleksi (Ras Laffan) doğrudan zarar gördü hem de küresel LNG gemi akışının %20’si kesintiye uğradı. - Özetin özeti: Hürmüz Krizi, şu an itibariyle henüz bir petrol krizi çıkartabilecek boyutta değil, ama gazda etkisi çok derin. Bugün bir ateşkes olsa ve gemi geçişi yarın normale dönse dahi, kaybedilen üretim kapasitesinin yerine konması (Rystad'ın projeksiyonuna göre) en az 5+ yıl ve 25 milyar USD yatırım gerektiriyor.
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Mustafa Altintas liked thisMustafa Altintas liked thisThe Neuromorphic Computing and Engineering (ICNCE 2026) will take place in Aachen, Germany, from June 28-July 2, 2026 (https://icnce-2026.de). Note that the conference was extended one day (June 28) for tutorials! Call for Abstracts closes April 3: The call for poster and oral contributions closes in one week. Please submit a one-page PDF of your abstract via the link below (https://lnkd.in/ejVJjxQd): Submission Deadline: April 3 (AoE) Notification of Acceptance: April 30 No proceedings: you are welcome to submit abstracts of previously published work. About ICNCE: ICNCE brings together a diverse community of researchers, from students to leading experts in academia, startups, and industry, to advance the understanding and engineering of brain-inspired computing technologies. The program spans electrical engineering, neuroscience, IT, materials science, physics, AI, philosophy, and ethics. Building on the success of the first ICNCE (2024), which gathered over 500 participants, this year's event will be held at the Eurogress Aachen, located in the heart of the historic city near RWTH Aachen University and Forschungszentrum Jülich (https://icnce-2026.de). We look forward to welcoming you to Aachen!Interdisciplinary event including Neuroscience, Microelectronics and Computer Science/AIInterdisciplinary event including Neuroscience, Microelectronics and Computer Science/AI
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Mustafa Altintas liked thisMustafa Altintas liked thisApple's AR glasses pipeline is hiding in plain sight - if you know where to look 🔍 Seven patent applications published this week quietly reveal a remarkably complete picture of where Apple is heading after AVP. The stack they're building spans every layer of the product: Optics manufacturing - A chip-on-wafer reconstitution process for SRGs, fabricating grating dies on silicon at DUV/e-beam resolution, then transferring them to high-index glass substrates. This is a direct answer to the yield and cost wall that has blocked every diffractive AR glasses maker so far. Display optics - A pancake lens module with matched polarization axes between display and lens assembly, geometric phase lenses for light redirection, and a low-visible + low-IR reflectance coating on the barrel housing. The ghosting suppression architecture is detailed to a level that suggests this is late-stage engineering, not early research. Form factor - Two separate patents address the glasses frame itself: a sealed U-shaped channel electronic sub-assembly with epoxy or cap enclosure (cameras, waveguides, controller - all inside the frame), and a flexible securement arm with a slotted-tube conduit routing audio from a rear speaker to a front-facing port near the ear. A larger battery fits proximally; the speaker sits distally as a counterweight. This is consumer glasses ergonomics, not a headset. Context awareness - A state-based operating mode system that distinguishes face-mounted, forehead-mounted, and torso-mounted states using IMU, eye tracker, and device configuration - adjusting camera frame rates, microphone beamforming, physiological sensing, and notification behavior accordingly. Tunable vision correction - A method for dynamically adjusting the optical power of the lenses based on eye tracking, such as detecting the user's gaze tilt or focus on specific holographic elements. Users can also manually control the optical power using gestures. This could eliminate the need for fixed prescription inserts. External social display - An outwardly facing display designed to present a user's facial features (like digital eyes) or status indicators to people nearby. It maintains social connection by revealing if the user is busy or engaged in an AR experience, adapting AVP's "EyeSight" concept to a wearable glasses format. What's the angle nobody is discussing? Apple isn't just building a lighter Vision Pro. They're assembling a complete, vertically integrated AR glasses platform - from SRG wafer fab to electronics packaging to context-aware OS behavior and dynamic vision correction - at a component maturity level that points to a product program well past concept stage. The WG SRGs patent alone solves the manufacturing cost problem that has stalled the entire industry. When Apple solves a manufacturing problem in a patent, they're usually already running it in a pilot line. Worth watching closely. 👓 #Apple #AR #XR #AugmentedReality #Waveguides #Smartglasses #PatentWatch
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Mustafa Altintas reacted on thisMustafa Altintas reacted on thisI was talking to an investor the other day. He asked questions about a company's growth opportunities, overall market trends and dynamics, and how those would affect the company. If he only asked if the company's management was a bunch of idiots, I could've saved him a lot of analysis time.
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Mustafa Altintas liked thisMustafa Altintas liked thisMany folks recognized the 50th anniversary of the microprocessor (the 8080) two years ago. Far fewer will mark this year as the 25th anniversary of the multi core microprocessor. The dual core IBM POWER4 was released in 2001. Coincidentally that year also marked the release of NVIDIA GeForce 3 - the first GPU with programmable vertex shaders which you might consider cores. Intel had already introduced multi-threaded CPUs, but threading was not initially popular (see “Why Threads Are a Bad Idea (for most purposes)” by John Ousterhout). Multi-core CPUs were immediately useful in servers where they were just an extension of multi-socket “scale-up” servers. Today server CPUs boast 256 cores or more in a socket. They are fed by enormous caches and a dozen channels of high-speed memory plus memory extending technologies like CXL memory and MRDIMMs. These cores are “brawny” cores – they do not compromise single thread performance and implement features like extensive speculation, bypasses, wide issue, deep buffers to look far ahead in instruction stream etc. Halfway through this period emerged the concept of “many-core” CPUs. These were meant explicitly for throughput and high-performance computing and collected many more “wimpy” cores in a socket. These wimpy cores had “single-core speed which is reasonably close to that of mid-range “brawny” cores". (following the wisdom of “Brawny cores still beat wimpy cores, most of the time” by Urs Hölzle). Intel’s Xeon Phi product line contained over twice the number of such wimpy cores than their contemporary server products. It turned out that these were neither fish nor fowl as the newly emerging GPGPUs were preferred for throughput computing. GPGPUs of course are now the mainstays of the AI revolution and revenue from their sales far outstrips server CPU revenue. The first dual core server CPUs sold for well over $1000 apiece. Today the server price per core is around $10. GPGPUs claim to have twenty thousand “cores” and their price per core is $1. The GPGPU core processes thirty-two bits of data while the CPU core routinely processes sixty-four bits and can do up to 512-bit vector instructions. A CPU core may consistently execute two instructions per clock while a GPU core takes multiple cycles per instruction. Adjust for all this and there may be logic to the 10X difference in price per core. Today both CPU and GPU cores are organized in clusters, and each cluster connects them to caches and memory in complex interconnect topologies like meshes. Recent clusters even reside on different pieces of silicon within a package. At the other extreme Cerebras locates all its cores on a single silicon wafer! Memory continues to be the biggest challenge to scale to more cores driving constant innovation. Happy Silver Anniversary Dual Core! You have come a long way.
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Mustafa Altintas reacted on thisMustafa Altintas reacted on thisAdamcağızın 45 sene önce kendi yazdığı makâlesine AI-generated demişler. Bu ne demek? Makâleyi eğitimde izin almadan kullanmışlar demek :)
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Mustafa Altintas liked thisMustafa Altintas liked thisThe results are out! 🎉We're number #1 in microcontrollers! Again and even stronger than before! 🚀 Our latest milestone: According to Omdia, we extended our leadership position in the global microcontroller market, with a 23.2% market share in 2025 📈. This is 1.8 percentage points more than in 2024. We’ve achieved this even though the overall MCU market declined –0.3 percent. We at Infineon Technologies consistently push forward — whether it’s engineering excellence, customer collaboration, or building solutions that truly make a difference. A few things I’m personally proud of: 🔧 How we keep raising the bar in technology and product quality 🧩 How our system‑level approach — compute, connectivity, security, software — helps customers innovate faster 🤝 How closely we work with partners to shape the future of mobility, IoT, and physical AI ...this all is of course driven by adapting to local markets and cultures. Also here in Greater China.
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Mustafa Altintas liked thisMustafa Altintas liked thisWell hot damn. The Onion was just named one of the 50 most innovative companies in the world by FastCompany. How did we do it? "How about the age-old strategy of: Write stuff your readers want to read? And if you do a good job, they pay you.” People want stuff made by other people that exists in the real, physical world, where we all actually live and breathe. Do more of that and it'll work. Anyway, we're coming for you next, AI perverts! Watch your six, NVIDIA!
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Marco Mezger
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NVIDIA picks Micron Technology for massive SOCAMM rollout 🤩 #Nvidia is preparing to enter a new phase in the memory market by planning to deploy between 600,000 and 800,000 SOCAMM modules in 2025. This initiative positions SOCAMM as a potential successor to high-bandwidth memory (#HBM). Although the initial deployment volumes are relatively modest compared to HBM, industry analysts suggest the move could trigger a wider transformation in the #memory and substrate sectors. According to reports from ET News and Wccftech, Nvidia has confirmed its intent to integrate SOCAMM into its next-generation #AI products, sharing projected order quantities with key #memory and substrate suppliers. The company's upcoming GB300 "Blackwell" platform will be among the first to adopt SOCAMM, alongside the AI PC Digits, unveiled during Nvidia's GTC 2025 conference in May. Nvidia initially tapped Samsung Electronics, SK hynix, and Micron Technology to co-develop SOCAMM. However, #Micron has emerged as the first memory maker to receive approval for volume production, outpacing its South Korean rivals in the race to support Nvidia's latest architectures. Thanks again to Amy Fan , Sherri Wang and DIGITIMES Asia for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eAjnXYQu #semiconductorindustry #semiconductors #technology #tech #innovation #usa #taiwan #geopolitics #datecenter #dram #ai #server #chip #ic #aiot
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Prakash Rashinkar
3K followers
*** New To Chiplets World: What I’d Focus On *** As a new engineer entering the world of chiplets, the learning curve is steep, but there are three areas I’d focus on first: 1.Understanding the interconnects. The core of chiplet-based SoCs is the inter-chiplet communication.Whether it’s UCIe, BoW, EMIB, or any other protocol, understanding how data moves between chips is crucial. If you don’t get how chiplets communicate, you won’t understand how your design will work in a multi-die system. 2.System-level thinking. Chiplet designs aren’t about optimizing individual chips—they’re about creating a coherent system. As a new engineer, it’s essential to look beyond the chiplet’s boundary and think about how your piece fits into the larger architecture. Understanding power, thermal, & communication interactions is key. 3.Verification from the start. The hardest issues with chiplets often surface at integration. Focus on building verification strategies early—both at the individual chipletlevel and in the full-chip system. A deep understanding of how chiplets interact will be your biggest asset. If you were starting fresh in the chiplet world, what would you prioritize?
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Pradeep Khannur
HCL Technologies • 9K followers
RF Basics: Down-Conversion Mixer A down-conversion mixer is a crucial component in radio frequency (RF) systems, especially in receivers. Its primary function is to lower the frequency of an incoming RF signal to an intermediate frequency (IF) or baseband frequency, making it easier to process and amplify. Here's how a down-conversion mixer works and why it's important: 1. The mixing process: A down-conversion mixer has three ports: an RF input, a local oscillator (LO) input, and an IF output. The RF port receives the high-frequency signal that needs to be down-converted. The LO port receives a steady, high-frequency signal generated by a local oscillator. The mixer combines these two signals using a nonlinear element (like diodes or transistors). This mixing process creates new frequencies at the output, including the sum (RF + LO) and difference (RF - LO) of the input frequencies. 2. Down-conversion to IF: In a down-conversion mixer, the desired output is the difference frequency (f_RF - f_LO) which is at a lower frequency than the input RF signal. This lower frequency is known as the intermediate frequency (IF). This process allows for better filtering of unwanted signals and noise at the lower frequency range, ultimately improving the signal-to-noise ratio. 3. Applications: Down-conversion mixers are widely used in receivers, particularly in superheterodyne receivers, which are common in radios, televisions, and cellular base stations. They are also essential in radar systems, satellite communications, and other applications requiring frequency translation for signal processing. 4. Importance in RF systems: Efficient signal handling: Down-conversion enables systems to process high-frequency signals more effectively by shifting them to a more manageable frequency band. Improved selectivity and sensitivity: Filtering is more effective at lower frequencies, allowing the receiver to better isolate the desired signal from interference and noise. Enhanced system performance: By reducing the frequency and facilitating filtering, down-conversion mixers contribute to overall system performance and efficiency. In essence, down-conversion mixers are key to making high-frequency signals accessible and manageable for various RF applications, contributing significantly to the performance of modern communication and electronic systems. 🙏🙏🙏🙏🙏
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Krishna Challa
2K followers
🔥 Multi-Core Design: The Hidden Battle of Power and Performance 🧠 Why Multi-Core? Single-core GHz race hit a wall. Heat and power skyrocketed. Multi-core scaled performance without chasing GHz. ⚡ But Here’s the Catch More cores = more complexity. Dynamic Voltage and Frequency Scaling (DVFS) became critical. Why? Because workloads vary. AI inference needs bursts. Idle cores need power gating. 🔍 DVFS Challenges Multiple voltage domains Per-core frequency tuning Timing closure across dynamic states IR-drop risk during voltage transitions 🏗 Power Delivery Challenges Dense power grids for 100+ cores Droop control during DVFS switching Package-level integrity for AI accelerators EM reliability under dynamic loads 🔥 Without mastering DVFS and power delivery, multi-core efficiency collapses. AI chips demand performance per watt , not GHz bragging rights. 💬 Your Turn What’s harder in sub-3nm era? DVFS complexity or power integrity? Comment below 👇 #VLSI #PhysicalDesign #MultiCore #DVFS #PowerDelivery #AIChips #Semiconductors #EDA #SoC
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Hugh O'Keeffe
Ashling • 4K followers
Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent
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Shivraj Dharne
HCLTech • 16K followers
HBM (HBMIO) and DDR are both DRAM technologies, but they are optimized for very different system goals. The differences span physical stacking, I/O interface, bandwidth, power, latency, packaging, and use cases. 1. Physical Stack & Packaging HBM Memory Stack • 3D stacked DRAM dies (4-Hi, 8-Hi, 12-Hi) • Dies connected using TSVs (Through-Silicon Vias) • Mounted on a silicon interposer next to the SoC • SoC ↔ HBM distance: millimeters DDR Memory Stack • 2D discrete DRAM chips • No TSV stacking (except internal DRAM techniques) • Placed on DIMMs or soldered on PCB • SoC ↔ DRAM distance: centimeters 2. I/O Architecture (Most Important Difference) HBMIO Interface • Extremely wide bus • 1024-bit per HBM stack (HBM2/2E) • Split into 8 independent channels • Low frequency • ~1–3.2 Gbps per pin • Massive parallelism DDR Interface • Narrow bus • 64-bit per channel (+ ECC) • Very high frequency • DDR5: 4.8–8.8 Gbps per pin • Few channels (2–8 typical) 3 . Bandwidth Comparison Bandwidth per Stack / Channel Memory Type-Bandwidth 1. HBM2-256 GB/s per stack 2. HBM2E-410 GB/s per stack 3. HBM3-800+ GB/s per stack 4. DDR5 (1 channel)-38–70 GB/s 4. Power Efficiency HBM achieves: • Lower I/O power • Better GB/s per watt 5. Quick Summary Table
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Nir Shafir
1K followers
It’s exciting to see chiplets go from concept to reality and even more exciting to see Arm playing such a key role in making it happen. Arm's ecosystem is leading the way: Amazon Web Services (AWS), Ampere, and NVIDIA are all building modular, disaggregated systems that unlock performance, efficiency, and flexibility. Proud to be part of the team shaping the future of compute. Check out this great read by Austin L.: https://okt.to/R2qch3
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DIYA SOUBRA
Arm • 8K followers
We’ve now seen the full spectrum of operator optimization, from kernels that are implemented purely in C, to those that leverage hardware instructions provided in architecture extensions, and finally to those that offload inference to a wholly separate processor. In future posts, we’ll explore how operators are encoded in .tflite files, and how the runtime ultimately invokes the underlying kernels. https://lnkd.in/e5xVMRHU
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Seung Wook YOON
Samsung Semiconductor • 1K followers
Samsung Reintroduces Exynos in Galaxy S26 Amid Comeback Push Exynos 2600, Built on 2nm Process, Aims to Overcome Past Heat Issues and Boost In-House Chip Adoption ....The Exynos 2600 is the first product to apply Samsung’s 2-nanometer process. Samsung claims the new chip improves central processing unit (CPU) computational performance by 39% and generative AI performance by 113% compared to its predecessor, while reducing heat generation by 30%. Benchmarks reportedly show the Exynos 2600 outperforming Qualcomm’s product in the Galaxy S26 Ultra model in three categories: classification, object detection, and natural language.... (source) https://lnkd.in/gzbg8PUA
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