691 questions
2
votes
1
answer
96
views
Oracle OFFSET/FETCH returns identical rows for different offset values when ORDER BY is non-unique
This is a follow-up to this question which shows the symptom but doesn't explain the internal mechanism.
Setup:
CREATE TABLE t (x INT, name VARCHAR(100));
INSERT INTO t
SELECT level,
CASE WHEN ...
3
votes
1
answer
137
views
Can (and should) a page table entry contain its own lock on RISC-V in Rust?
On RISC-V, A page table entry, which is the size of usize in Rust, has an RSW field, which is 2 bits wide. This field is supervisor defined (e.g. the kernel can use it as it pleases). Could one of ...
- 417
1
vote
1
answer
133
views
Does Intel CPU have instruction for paging translation result
I wonder if Intel (and Intel compatible) CPUs have an instruction (for diagnostic/debugging purposes) which, for a given linear address, returns the result of paging translation (i.e. the ...
- 184
3
votes
2
answers
153
views
How can I correctly load the kernel to its canonical high address space
I am working on a small os with a custom boot loader targeting BIOS. For this, I need to map the kernel to its canonical high address space (0xFFFFFFFF80000000) and jump to its entry point.
For this, ...
- 133
0
votes
1
answer
118
views
Paging in x86: what exactly is divided into pages, and why does the linear address behave differently depending on paging?
I'm trying to fully understand how paging works in the x86 architecture when segmentation is also enabled.
I have a couple of questions:
Does paging divide the logical memory (the selector + offset ...
- 15
5
votes
1
answer
170
views
Zero-initialized array keeps having non-zero values [closed]
I am encountering something extremely strange on my system right now.
#include <cstdint>
#include <iostream>
constexpr size_t N = 1l<<31;
int main() {
auto buf = new int64_t[N]{...
- 2,123
2
votes
1
answer
159
views
Why does kernel always allocate N-1 2MB pages?
I turn on the huge page option in linux using THP, Transparent Huge Page. And I wrote some simple code to check whether it really allocate huge page or not.
As a result, it actually does but something ...
- 344
1
vote
1
answer
146
views
How to enable paging in x86 Protected Mode
I'm progressing along developing my OS, and I recently implemented a virtual memory manager that handles paging. I used 2 Page Tables: (1) to identity map the first 4 MB and (2) to map the kernel (...
- 31
0
votes
1
answer
130
views
Why is a memset causing my higher-half kernel to page (interrupt 14)?
Currently, a memset to kernel_dir is causing my kernel to page fault. The kernel is a higher-half kernel, and is mapped to 0xC0000000 in virtual memory.
#include "paging.h"
#include "...
- 129
1
vote
0
answers
113
views
KVM crashes with General Protection Fault when enabling paging in my 32-bit kernel. OSDEV
I'm writing a 32-bit OS kernel with support for PAE paging. When I enable paging with mov %eax, %cr0 (setting the PG bit), the kernel works fine under QEMU with TCG, but crashes with a General ...
1
vote
1
answer
84
views
How to receive properly a physical address after paging
I have implemented basic paging (partially based on OSDev) and successfully mapped memory pages. However, I am facing an issue where I can no longer access the framebuffer address stored at physical ...
0
votes
1
answer
126
views
Instruction Idempotence on Page Faults
I was reading the lecture notes here about Demand Paging. The author states that:
Restarting process execution after a page fault is tricky, since the fault may have occurred in the middle of an ...
- 1,212
0
votes
1
answer
138
views
Page offset on large page support on x86-64 system
I have a question while reading the paper, Supporting x86-64 address translation for 100s of GPU lanes.
The x86-64 ISA has extensions for 2 MB and 1 GB pages in addition to the default 4 KB page size....
- 344
2
votes
0
answers
88
views
How do I resolve the recursive dependency in my page frame allocator (custom OS)?
I’m developing a custom OS and facing a chicken-and-egg problem with my page frame allocator. I need to map a specific page, but if the corresponding PML4 entry is NULL, I must allocate a PDPT. ...
- 292
0
votes
1
answer
125
views
How page alignment & page borders affect performance when traversing & reading objects
I ran a test to better understand how pages affect performance when traversing & reading objects in memory but I got the opposite of what I was expecting. I'm hoping someone can explain this ...
- 191