I’m working on a DDR4 PCB layout and want to confirm the allowed rules for bit swapping, byte lane swapping, and nibble swapping, especially when ECC or CRC is enabled.
From what I understand so far:
Bit swapping within a byte lane (e.g., DQ0 ↔ DQ3) is generally allowed if CRC is disabled.
Byte lane swapping is allowed if the entire lane (DQ[7:0], DQS, DM) moves together.
Cross-byte swapping is not allowed.
In some DDR4 cases (especially x4 devices), cross-nibble swapping (e.g., swapping DQ1 with DQ5) is not allowed — each 4-bit nibble must stay intact.
ECC (extra 8-bit lane for error correction) follows the same swapping rules as normal data lanes.
CRC (real-time error check in DDR4 protocol) is unrelated to ECC but forbids bit swapping within a byte lane because the CRC calculation depends on fixed bit positions.
My questions:
Is my understanding correct for DDR4, including the cross-nibble swapping rule?
Are these restrictions the same for x4, x8, and ECC configurations?
Does enabling CRC mode always forbid bit swapping within a byte lane?
Any JEDEC references or practical design experience would be appreciated.
