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I bought a book called "Computer Time Travel: How to build a microprocessor from transistors" where as one of the first exercises the author builds a clock module for the processor.

He gives this schematic:

Clock Schematic

This is simply not working for me: The output voltage is around 0.9V (measuring with a multi-meter shows a constant value) and the 74LS04 becomes so hot that I remove power rather quickly. This is also why I haven't analysed with an oscilloscope yet.

I'm largely self-taught, and although having completed Ben Eater's 8-bit computer I'm still a beginner in many respects, so I may be making some silly mistake.

This is my current breadboard implementation:

Edit: I do have pin 7 connected to ground. It's missing on the pictures. Sorry.

enter image description here

enter image description here

Edit 2: Updated image

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On a side note, I successfully implemented an alternative schematic that uses a Schmitt trigger (74HC14). So while I could use that instead, I would like to know why the above circuit isn't working.

What I would really like to understand is, how is the circuit expected to produce a clock signal? Trying to understand its behaviour over time, I find myself wondering how it even enters a defined state, since the inverter inputs aren't tied high or low. If the first inverter's input happens to float, will the random output value slowly charge the capacitor until the second inverter's input goes high (just guessing)?

And then what does the capacitor's charge/discharge cycle look like - does it discharge back through the first inverter's output? To that inverter's ground, or out of its input, or ... ?

Would much appreciate if anyone can explain how exactly this circuit works.

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    \$\begingroup\$ So if your circuit photo has a missing wire that's really there, then something else might be different as well. I can't see if it is a 74LS04 or some other type. \$\endgroup\$ Commented Nov 19 at 22:28
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    \$\begingroup\$ Measure the voltage between oin 14 and pin 7. It should be positive 5 V. If it's negative or more than 5 V, that's your problem. \$\endgroup\$ Commented Nov 19 at 22:39
  • \$\begingroup\$ the marking on the chip says "SN74LS04N" SN is Texas Instuments and "N" is the package type, so it's the right chip. \$\endgroup\$ Commented Nov 20 at 2:37
  • \$\begingroup\$ This 2-gate design can sometimes fail to start, it needs a good switch-on transient to give it a kick. The 3-gate design always starts (first gate as inverter, next 2 gates as a latch) \$\endgroup\$ Commented Nov 20 at 8:21
  • \$\begingroup\$ I had trouble getting this circuit to work too. Did you get your problem resolved? \$\endgroup\$ Commented Nov 23 at 19:47

3 Answers 3

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The circuit is a simple oscillator. Just not a very good one, as it runs the polarized capacitor with inverted polarity half of the cycle and may push too large voltages to the inverter input, but nevertheless tries to be an oscillator.

You have to first see that a logic gate has valid input voltage ranges for high and low states, and the output is defined by that. In between there is a range of input voltages that should be avoided because in practice a logic gate is simply an amplifier which clips to regenerate a clamped output from input, so somewhere in between there is the switching threshold and around it the inverter behaves like a linear amplifier.

The second inverter alone has a resistor between input and output. This biases the gate to sit right at the threshold, so even small amplitude changes on input cause large voltage changes.

The first gate simply makes an opposite state out of the second gate. So together they charge and discharge the capacitor.

When second gate output is high, first gate output is low, and capacitor charges through resistor. When charged enough the threshold to change to opposite state is reached so then the gates discharge the capacitor until again threshold to change state to charge it is reached.

The startup transient phase is rather arbitrary, on powerup the cap can be assumed to have 0V over it and the gate thresholds are never exactly equal in real life, so the circuit biases itself and charges the cap and the oscillation builds up to steady state.

And why it does not work can't be seen from photos. Maybe chip is damaged. Maybe missing bypass caps cause the chip to work poorly.

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    \$\begingroup\$ Do you mean to say it's "just not a very good one"? Wording it as "not just" implies that it is a good one and more, but the rest of your description suggests that's not what you intend. \$\endgroup\$ Commented Nov 20 at 2:47
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The chip getting hot is a symptom of something being seriously awry.

Either an output shorted to a supply rail, reversed supply voltage is applied or you have a bad chip.

I can’t see an output shorted. It’s not possible to tell what polarity supply voltage is connected. Even a momentary reverse connection can damage the chip permanently and result in the symptoms you are seeing from that point forward, even when the polarity is corrected.

As to how it is supposed to work, imagine the node at the output of the left inverter going from 0.2V to 3.6V and back again. When the capacitively-coupled input to the other inverter gets to about 1.5V it will switch. So in the case of the 0.2V to 3.6V transition, the other inverter input will go from 1.5V to 4.9V. The capacitor will discharge through the 2.7k resistor (minus the input current which is a few hundred uA).

When it gets down to about 1.5V it will switch again, with the left inverter input going from 3.6V to 0.2V, so the input of the right inverter will go from 1.5V to about -1.9V, except the input will conduct when it goes below ground by about 700mV (due to the isolation diffusion parasitic diode) so it will start charging from about -700mV to 1.5V through the 2.7k resistor (and now plus the input current). As a result of all that likely you'll get a pretty asymmetrical square wave. It's also abusing the input so at the very least make sure you have a bypass capacitor (100nF to 1uF from GND to Vcc on the chip) and it wouldn't hurt to add ~50 ohms in series with the capacitor.

The capacitor will see maybe -1.3V, which is acceptable for most common 16V or greater electrolytics. It's a bit dodgy for a 10V or 6.3V rated unit.

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Try increasing the resistor to 2.7K like it says in the book.

This circuit puts current though the input protection diodes. try adding 33 ohms in series with the capacitor to reduce this current,

I got it ti run in simulation but only after making those two changes

schematic

simulate this circuit – Schematic created using CircuitLab

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