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I am a beginner designing my first custom PCBA based on the Xilinx Zynq-7000 SoC (specifically the XC7Z020-1CLG400C).

While reviewing the decoupling capacitor requirements in the Zynq-7000 SoC PCB Design Guide (UG933 v1.13.1, March 14, 2019), I checked Table 3-1: "Required PCB Capacitor Quantities per Device (PL)". For the CLG400 Z-7020 package, Xilinx specifically recommends 1x \$330\ \mu \text{F}\$ capacitor for the VCCINT rail.

enter image description here https://docs.amd.com/v/u/en-US/ug933-Zynq-7000-PCB

However, I am using the Digilent PYNQ-Z1 development board schematic as a reference. Looking at their FPGA Power schematic for VCCINT, they used a \$100\ \mu \text{F}\$ capacitor (C131) instead of the recommended \$330\ \mu \text{F}\$.

enter image description here https://files.digilent.com/resources/programmable-logic/pynq-z1/pynq-z1-sch-f0.pdf

Since I am new to PCB design, I have a few questions about this discrepancy:

  • Why did Digilent choose not to fulfill the strict Xilinx requirement here? Is there a technical reason why \$100\ \mu \text{F}\$ is sufficient for this specific board?
  • Does this deviation matter? As a beginner, should I strictly follow the Xilinx UG933 guidelines and use a \$330\ \mu \text{F}\$ capacitor, or is it safe to replicate the dev board's \$100\ \mu \text{F}\$ choice?
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Follow the published Xilinx UG933 guidelines for your device. If your board had unreliable behaviour, it would be little comfort that Digilent's worked.

The UG933 capacitance values are to cover all FPGA functions being used (I/O pins loaded to max. current and switching at max. frequency, across full temperature range and voltage range. Fit them all, which at worst gives you the option to experiment with lower value capacitance within your usage parameters of load currents, functions used and temperature.

The FPGA device has the small high-frequency decoupling capacitors internally, within the device package. Try to have as short connections as reasonably possible between the external bulk capacitors and the FPGA power pins.

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Why did Digilent choose not to fulfill the strict Xilinx requirement here? Is there a technical reason why 100 μF is sufficient for this specific board?

You forgot to check other places: -

enter image description here

That's 300 μF when you take into account the three instances of those capacitors on that power rail. Plus all the other localized capacitors.

Neither do the 100 μF caps need to be that close; the capacitors close to the pins are vital but, bigger ones (like 100 μF) can be distributed around the device with less onerous rules.

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  • \$\begingroup\$ I like to stick to answering your specific question rather than anything else btw. \$\endgroup\$ Commented Mar 18 at 0:57
  • \$\begingroup\$ Hey Andy, another quick one: I noticed UG933 uses 'Z-7020' in the tables, but the chip itself is labeled '7Z020'. Do you know why Xilinx swaps the '7' and the 'Z' like that? Just curious if it’s a typo in the docs or just how they shorthand the series. \$\endgroup\$ Commented Mar 18 at 9:07
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    \$\begingroup\$ @MarcoMoldenhauer sorry but this question has been closed by virtue of you accepting an answer. Raise a new post is the best way. \$\endgroup\$ Commented Mar 18 at 9:51
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By now you probably think you have your answer, and you’re satisfied… Not so fast, Marco.
I'm surprised that nobody brought up the DC bias derating yet.

The 100μF capacitors are ceramic capacitors. Find the part number for your 100μF capacitor and look-up DC bias derating for them. The curve may be in the datasheet. It will look similar to this one.

DC voltage derating curve DC bias curve for a ceramic capacitor

This curve is for C3216X5R0J107M160AB made by TDK.
It’s a reasonable ceramic 100μF capacitor 6.3V X5R in 1206.

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    \$\begingroup\$ Have a look in UG933. It doesn't specify a capacitance for each FPGA load rail, it specifies a number and value of capacitors. It gives example X7R/X5R ceramic parts and tantalum parts, with the characteristics required by alternative parts used. \$\endgroup\$ Commented Mar 18 at 7:07

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