Trivial counterpoint: run an SoC through a long spaghetti wire. The onboard capacitance resonates against the, let's say it's a hearty 10µH here, giving a Zo of maybe 2Ω against the onboard capacitance of say 2.5µF.
The peak impedance of this LC network is determined by its loss. There may be parallel and series losses in either element. Let's suppose (without loss of generality) that it's ESR. We make the wire thick enough that its ESR is negligible. That leaves the SoC. It's probably low ESR for two reasons: 1. a low impedance is demanded for functional purposes; 2. low-ESR materials are used (copper interconnects (on die and interposer), ceramic capacitors).
Note that the on-die power network may be constructed as layer(s) of grids, thus using the SiO2 as dielectric to surprisingly high capacitances (many nF, maybe even a few µF). SiO2 has famously low losses; loss would be limited by the metal layers (thickness and area).
Probably the ceramic capacitors dominate losses, typically having a Q factor in the 30 range (LF asymptotic). It seems unlikely they would use anything other than type 2 (ferroelectric) dielectric; other types have lower dielectric constant, and still lower loss.
It also seems unlikely they intentionally reduce interconnect thickness/width, to increase ESR. In the intended application, ceramic cap ESR is high enough to dampen oscillations between nearby capacitors. But only to a point.
If we increase the (electrical) distance to nearby capacitors to a whole 10µH (equivalent to several meters of wire), we get an impedance peak of Q*Zo or 60Ω at 32kHz.
Presumably, the SoC (if it starts at full some-GHz clock speed) could complete a few function calls in that time, perhaps even task switches. It won't take much variation in load, in data flow or execution path or instruction load, let alone sleeping into a task switch (more or less, a minimum to full load step), to ping an impedance that high.
The resonant frequency is low enough, it might even cause damage on startup. Notice that a regulator enabling in < 100µs, even if it has controlled slew rate, will excite some ringing in this network. Startup overvoltage could cause destruction.
While this is an obviously contrived situation, the point stands: the environment beyond the chip of course cannot be ignored.
Indeed we follow similar calculations to figure out what the limiting inductance between chip and local bypass is, to plan the PDN. These calculations are left as an exercise for the student. :)
