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I am developing a system with multiple (four) distinct PCBs containing devices that need control from a central MCU via SPI plus a smattering of gpio and other slower signals. My plan is to connect them all with a common backplane PCB.

I need to choose connector hardware and understand any special layout or driver requirements. Boards, including the backplane, will all be four layer (SIG / GND / PWR / SIG). The SPI bus target maximum speed is 25 MHz. Which puts it right on the edge of "high speed design".

On a given board, SPI traces may be up to 200mm. Over the backplane, approx 60mm. Boards will have a buffer IC so they do not form an enormous SPI "star".

Backplane Connectors:

If I search for high speed backplane connectors with a specified impedance or high bandwidth, they either (a) cost a lot or (b) have very fine pitch SMT footprints or both.

My cost target is $5 or less for each connector. 4 boards x 2 (F + M halves) means I need 8 connectors total.

I am not averse to SMT but the pads need to be accessible (I assemble via hot air pencil, I lack a reflow oven) and pin pitch of 1.27mm+ is preferred. Shielded SMT connectors also advertise multi-GHz performance which seems like overkill. I don't need to pay for 10GHz performance, but I haven't seen anything advertised with a 100 MHz (say) target.

Mechanically I have a fair bit of width to work with per board but boards will be packed fairly close together in the depth direction; total target depth is 55mm. So longer/thinner connectors are better than a more square shape.

From a mechanical and cost standpoint, 64-pin DIN 41612 (Eurocard) connectors (type B / dual row) are attractive. But they specifically call out a 3 MHz max design speed. This feels like undershooting; I have driven SPI point to point at 10 MHz from an MCU on a breadboard over flying wires.

Main question here: Am I crazy to think this connector will work? Is there something else worth looking at instead? And do I do anything to impedance-match the pcb traces to the pin connections?

Pin arrangement

I will have plenty of pins for GND, although not so many that I can just bury each of the SPI signals in an isolated "C" of GND pins built over the two rows.

There will be eight SPI chip select pins; I was planning to multiplex their use with four "board select" pins as well. Since CS and BS signals will be frozen during an SPI transaction, can I use these as some of the "reference shield"?

That is, assuming "g" is GND, "c" is a CS or BS signal, and "S" is a main high speed SPI signal like MOSI or CLK, is something this a smart / feasible way to do the pinout?

g S c S c ...
g g c g c ...

Driver and termination

I planned to have SPI signals buffered at the entry point to each board, e.g. via SN74AHC245. The CS pins would be similarly buffered, with a "board select" signal disabling the CS buffer when CS signals are relevant to a different board.

There will unavoidably be stubs coming off the backplane to each driver IC although it will be fairly short / close to the connector.

Some advice I'd seen elsewhere is to have SPI devices wired point to point and then use series termination. p2p is not possible on a bus, it's necessarily a kind of star / daisy chain-ish configuration. If the driver chips (the '245s) have CMOS / high Z inputs, is the issue with the stub or with the receiving IC pin / transistors? If the latter can I use the DIR and OE pins of 74AHC245 to make it look like the '245 input is effectively disconnected from the trace when not in use? Or does it not matter? (Short of a relay, I can't mechanically disconnect the deselected boards.)

My default idea for driving the bus is the output of another SN74AHC245 with a source-side series resistor as terminator.

On a given PCB, the input driver / buffer's output will fan out to up to 8 SPI devices. Daisy chain them, use source termination to 50 or 100 ohm, and control trace impedance to the same? Or don't worry?

With all of the above implemented, the connection chain would be:

MCU MOSI/CLK output GPIO - SN74AHC245 - 27R - backplane c'tor - '245 (x4) - 27R - (board-specific devices x1-8)

... Or do I need parallel termination in some place(s)? I'm not sure how to do this with multiple devices on a board or bus though.

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The board is on the edge of being a high speed design, but first it must be analyzed if it is or if it isn't, and based on what it should be decided.

You say the SPI is used at 25 MHz. As signals can be approximated to travel at 0.66 times speed of light on a PCB trace, it means clock has wavelength of 8 meters. That does not sound so bad, but by applying some rules of thumb, every trace longer than 0.8 meters is a high speed design. Except that the clock is not a sine wave, but a square wave. So different calculation method is needed.

You use a 74AHC245. The datasheet says that at 5V the inputs must switch faster than 20ns/volt or the operation isn't guaranteed. Also at 5V, the chip outputs have a slew rate of 4ns typically, but it could be 1ns. 4ns slew rate translates to approximately 88 MHz bandwidth, so anything longer than 22cm is a transmission line and requires high speed design.

So each board alone is very close for requiring good impedance control if you have 20cm SPI traces.

Basic pin headers have been used between boards successfully and you could use 2.54mm or 1.27mm pitch pinheaders, single or dual row, in any angle you find suitable between boards.

For the impedance, you don't need to match the connector impedance to PCB, as generic pinheaders don't really have controlled impedance. More important is consistent PCB trace impedance, and 4 layer boards help with that.

The AHC245 also isn't super strong so it might have problems driving 50 ohm PCB trace impedance, so if possible, make it a bit higher.

Series termination at the source helps too, but you might prepare for AC termination at the receiver. But too much source termination in conjunction with the trace capacitance means slower RC waveform, and you must be sure that at the receiving chip input must transition at the rate the chip requires.

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  • \$\begingroup\$ Thank you. Why is the pin header impedance not an issue? Board-to-board pins just won't make meaningful reflections? Is there a rule of thumb for picking a "good" board impedance? Absent other constraints at this point I could go to 100 Ohm... or higher? SPI will be running at 3.3V. And, by default I reach for AHC logic b/c the relatively weak drive strength means less ringing to damp... but I could use something else like 74AC245 if the +/-12 mA (rated@ 3V) strength is more appropriate for this application. \$\endgroup\$ Commented 2 days ago
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    \$\begingroup\$ 74AHC245 are 125 Ω max @ 25 ℃ so a 100 Ohm bus will be well damped. Alternative also 74AHCT245 with input threshold at 1.4V and 55 Ω max @ 25'C \$\endgroup\$ Commented 2 days ago
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    \$\begingroup\$ @AaronKimball The connector is so short that the mismatch caused by connector is not that significant. Assuming electrical length for connector is 2cm, that's ~10x shorter than the 22cm rule of thumb for a 4ns signal. Assuming you pick slow and weak enough types of chips, or use source termination to reduce slew rate, you barely need to consider impedance. Pin headers are used for multi-hundred MBps differential communications at around 100 ohms differential impedance, and e.g. few hundred MHz of analog video adequately runs over D-Sub connectors at 75 ohm single-ended. \$\endgroup\$ Commented yesterday
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Back in the day (1990s), I worked for a company whose primary product was a piece of telecom equipment that was constructed as a rack of cards in a 3-U rackmount chassis (17" wide). A backplane ran across the width of the box about 3/4 the way back, with logic cards plugged into the front and I/O adapter cards plugged into the back.

Physically, the logic cards used the same card-edge connectors as the STD bus, with 56 fingers, but the signal assignments were completely proprietary.

I needed to come up with a way to communicate1 between a "master" card near one end of the chassis and all of the other "channel" cards, using at most 4 signal pins that we could identify as "spares". I looked at both I2C and SPI, and ended up inventing my own "SCB" (Serial Control Bus) protocol that implemented what I saw as the best features of both: separate "data in" and "data out" lines like SPI that allow higher speeds with no turn-around issues, but device addressing built into the protocol like I2C.

The backplane already had a continuous 6.176 or 8.192 MHz clock signal, so I just needed three additional pins — the aforementioned data in and data out, plus a "sync" signal that marked the beginning and end of bus transactions. The master card and most of the channel cards had small Actel FPGAs that implemented the protocol hardware, but it was simple enough that it could be done in TTL or a CPLD if necessary.

Anyway, getting back to your own project, I mainly wanted to say that the system generally worked quite well. The biggest problem we had was getting clean edges on the clock — since it was a pre-existing signal, I had no control over things like crosstalk with other nearby signals. I ended up adding a glitch filter inside the FPGA to clean it up.

And I agree with the others regarding the DIN 41612 connectors — they should work fine in an application like this. You've already identified the necessity of buffering on the cards to keep the backplane stubs short. Just keep in mind that the total end-to-end propagation delay will be a factor in how fast a clock you can use.

1 This was configuration and status information, not payload. The idea was to add a remote control capability to cards that up to this point had been configured by DIP switches and showed their status on front-panel LEDs.

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I was going to recommend DIN 41612, but you already know about them. Back in the day, VME and VXI bus backplanes routinely pushed 50 MHz signals. What is your worst-case pin count for a daughter card? Also, worst-case current?

Another option is the PCI bus parts used in IBM PC clones. The bus started out at 33 MHz, but grew to 133 MHz.

https://en.wikipedia.org/wiki/PCI-X

I don't recall if PCI-X and PCI Express used the same connector types, but they both supported 100 MHZ-plus.

Unless you need a ton of pins, I would stay away from cPCI (money) and VPX (VITA47) (more money).

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  • \$\begingroup\$ Assuming I've mapped everything out upfront, it fits in 48 pins. I have lateral space available so a 64-pin 41612 would give some headroom. Does PCI have male connectors? I thought it needed gold fingers on the daughterboard. (JLCPCB can kind of make prototypes w/ gold fingers but their ENIG coating is flimsy.) \$\endgroup\$ Commented 2 days ago
  • \$\begingroup\$ @AaronKimball Have you asked JLCPCB if they can do electroplated gold suitable for a PCI connector? Or do they only offer that for production quantities rather than prototypes? How durable would you need it to be for a prototype? \$\endgroup\$ Commented 10 hours ago

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