Questions tagged [pll]
PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.
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PLL not locking after CPLD change
I am currently working on a redesign of one of my older PCBs. On this PCB there is a HEF4046BT used as a PLL. I needed to exchange the CPLD, which is used as a frequency divider between the ports ...
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Programming-free solution to Generate 50 MHz Clock from 25 MHz crystal
I am looking for an IC that can generate a 50 MHz clock from a 25 MHz crystal.
I know how to do this with a microcontroller with an internal PLL, but I am looking to do this with a standalone IC that ...
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How do I connect a PLL sensor on transformer output with two secondary windings to a diode rectifier load?
Background:
I am working on a project of modernizing a system for a lead acid battery charger. I will do this with a Vienna rectifier, that needs the current angle, that I get from a PLL, for control.
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ADF4001 Programing And Testing
I trying to program the ADF4001 in order to make a PLL with an N counter and R counter of 1, but I have no output on the CP pin. I am unsure if it's the way I am programming the chip or the layout I ...
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Why is time constant of PLL by rule of thumb higher than the reference period?
Why do we generally say that the time constant of a PLL (\$\tau\$) must be 10 to 5 times higher than the \$T_{\rm IN}\$ of our reference frequency?
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Simulink PLL model shows different settling time than theoretical calculation
I'm modeling an Integer-N PFD/CP-based PLL in Simulink based on Example 3.2 of Rogers' book (Integrated Circuit Design for High-Speed Frequency Synthesis), but I'm not getting the same results. In the ...
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Flicker Noise and Phase Noise [duplicate]
In the formula above , it is given that jitter due to flicker noise = n x timining variation / t
since n/t = 1/f , shudnt the formula be timing variation / f then instead of timing variation * t
(...
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Flicker and Noise Floor
https://www.ti.com/lit/an/sbaa661/sbaa661.pdf?ts=1745596081730&ref_url=https%253A%252F%252Fwww.google.com%252F
This document talks about the impact of slew rate of reference source on PLL. Few ...
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PMU vs PLL in power system
I have been reading a lot about power systems lately, and am confused regarding the difference between phasor measurement units and phase locked loop? Firstly, are they different. PMU as I have read ...
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Gowin 1K PLL Calculation Happy Accident
I have been trying to create a 6 MHz signal output from a 27 MHz system clock using a PLL on the Gowin 1K FPGA.
As can be seen ...
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MAX 10 FPGA constraint problem
I'm working on specific multi-rate, multi-modulation modulator using a MAX 10 FPGA. The design consists of linear chain of switchable FIR filters.
I faced a problem. When testing modulator on output, ...
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Si5351 Constraints I don't understand
I'm following this tutorial on si5351, with the goal to generate variable frequency range (eventually with two clocks in quadrature).
Anyway the tutorial is quite interesting, but it give some ...
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Modeling loop bandwidth of PLL loop filter
I have a PLL circuit which produces a range of frequencies. I need to design a new circuit based on another PLL synthesizer from Analog Devices using the existing design as a reference.
Analog Devices ...
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LTspice: Timestep Too Small
I am trying to simulate a PLL using dflops as my phase detector, but the simulation seems to crash with the error "timestep too small ; trouble with dflop-instance a2"
I've seen a different ...
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PLL in Phase lock but not at 0 degrees
I have a PLL that is meant to synchronize a VCO to a reference signal, but the VCO is 90 degrees out of phase with the reference. How can I fix this to be precisely in sync with the reference signal?
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