Questions tagged [vhdl]
VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.
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Can I determine if two (clock) signals are the same?
I'm writing a small VHDL component with two clock inputs, because the two interfaces it presents might get used from different clock domains.
If the component is used in a context with a single clock ...
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Integer Increment Problem in Hardware - VHDL
I am trying to work with a transceiver and having some hard time figuring out why an integer signal isn't updating on a FPGA when I put a reset condition.
Basically, the following process runs with ...
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Using statemachine type as array index - VHDL
For practice I have made a statemachine that should blink some LEDs in turn. I have made a statemachine to go through 4 states. My plan is to use the statemachine variable (LED_STATE) to select which ...
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VHDL - exceeded beyond integer type range
I have a very simple piece VHDL of code that was created under Vivado 2025.1. It gives me this warning:
[Synth 8-11585] Evaluated value has exceeded beyond integer type range
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PLL not locking after CPLD change
I am currently working on a redesign of one of my older PCBs. On this PCB there is a HEF4046BT used as a PLL. I needed to exchange the CPLD, which is used as a frequency divider between the ports ...
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What capital pi notation means in VHDL literature
An exercise in one of VHDL learnbooks asks to write a VHDL model implementing the following function $$ F(A, B, C, D) = \Pi(3,2) $$
But the authors don't explain what the capital pi means here. Is it ...
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BCD Counter False Start
I am trying to implement a Digital Stopwatch in Xilinx ISE using four 4-bit Mod 10 BCD Counters and two 3-bit Mod 6 BCD Counters
They are cascaded in the following way:
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In VHDL processes, statements are executed sequentially BUT that's not the whole story? [closed]
I've been taught that statements in processes are executed sequentially, like in software programming, but it turns out it really isn't like that because apparently signal value assignments happen ...
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Issue VHDL custom AXI4-STREAM IP generating TLAST
I'm currently debugging a custom AXI4-Stream RTL module that I'm using to transfer data from the XADC to the DMA on a Zynq SoC. The goal of this module is to collect a fixed number of samples (...
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FPGA - Designing a parallel scrambler that also unscrambles to return original data
More details given below. My main question is, should the scrambler return the original data if the scrambled input is passed back into it? And if yes, what logic am I missing?
Apologies for the poor ...
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Quartus internal oscillator
I have managed to implement the internal oscillator in the CPLD MAX II: EPM240T100C5. From what I can see it can be set to either
I have used the wizard to generate the code for 5.56 MHz. The files ...
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Creating a single-element integer_vector
I'm trying to create a constant or variable of type integer_vector with a single element, where the value comes from a parameter of a function. The following ...
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VHDL counter simulation abnormal start
I would like to get an explanation or be directed to a specific literature to understand the behavior below. I am using Digilent NEXSYS-A7-100t with AMD Vivado and running post-implementation timing ...
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Different implementation between FPGA and CPLD?
I have this very simple VHDL code that should implement a flip-flop with asynchronous (active low) Set and Reset.
The clock (Clk) has no oscillator connected to the pin, only an input I can toggle ...
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Vivado `ERROR: [VRFC 10-9239] null index range cannot have an index value` when using nested conditional VHDL generate statements
I want to design a simple multiplier from gates, without any processes. It shall be capable of signed and unsigned as well as vectorized and non-vectorized multiplications.
The multiplication happens ...
