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I'm following this tutorial on si5351, with the goal to generate variable frequency range (eventually with two clocks in quadrature). Anyway the tutorial is quite interesting, but it give some constraint as assumption I can't find in the datasheet. Let's consider the formula they use to calculate the output frequency (to use same language here): enter image description here

Where FMD is the feedback multisynth divider and OMD the Output multisynth divider. They state:

The VCO frequency can only be from 600 MHz to 900 MHz. Yes, over-clocking is possible, and so is under-clocking, to extend the output frequency range beyond 2,3 kHz to 200 MHz. But let’s leave this for now. The FMD ratio can be from 15 + 0/1 048 575 and to 90 + 0/1 048 575, i.e. a = 15, b = 0 and c = 1 048 575 to a = 90, b = 0 and c = 1 048 575. Please remember that c can never be zero (0), as this will violate fundamental math principles. The OMD ratio can be 4 and from 6 to 2048. Please remember that f can never be zero (0), as this will violate fundamental math principles. The R divider can only be 1, 2, 4, 8, 16, 32, 64 or 128. If the output frequency is above 150 MHz d is always 4. If the output frequency is below 500 kHz R should be used, i.e. higher than 1.

A part from the frequency constraint, and the 1 048 575 constant (due to 20 bit), what is the explanation to the constraints below? Where these limits are found?:

  1. The FMD ratio can be from 15 + 0/1 048 575 and to 90 + 0/1 048 575, i.e. a = 15, b = 0 and c = 1 048 575 to a = 90, b = 0 and c = 1 048 575.
  2. The OMD ratio can be 4 and from 6 to 2048

To clarify even more the question: the article does non mention how these constraints cames from, and, with my knowledge, I can't find mentions of such limits in offcial datasheet.

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    \$\begingroup\$ Is there a question there? What frequency do you want to generate? \$\endgroup\$ Commented Feb 19, 2025 at 8:22
  • \$\begingroup\$ @Neil_UK yes, I added the missing question mark, sorry for being unclear \$\endgroup\$ Commented Feb 19, 2025 at 10:17
  • \$\begingroup\$ But it's still not clear what you are asking. You ask where you can find the constraints and then proceed to reveal them as numbered items 1 and 2. What are you really asking? \$\endgroup\$ Commented Feb 19, 2025 at 10:27
  • \$\begingroup\$ @Andyaka I tried to add some more in the question. I want to understend deeply the behavior, I can't find reason for the constraint 1 and 2 in the datasheet \$\endgroup\$ Commented Feb 19, 2025 at 10:43
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    \$\begingroup\$ @FelicePollano Try Skyworks app note AN619, in conjunction with the data sheet. Constraints like denominators not exceeding a certain width are merely how many register bits have been provided. Constraints like divisors = 4, 6 or up to lots are just the way the divider has been implemented, that 2, 3 and 5 aren't available, often speed and complexity are traded for limited function. You would have to go into the design of the individual dividers and their speeds to understand 'why'. I have a patent for making a low noise divider run fast, with low power, in a small area, because it's cheaper. \$\endgroup\$ Commented Feb 19, 2025 at 12:17

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Manufacturers of complex circuits often provide 'Application Notes' in addition to their datasheets, which go into more detail on how to program and apply their parts, and often a lot of general background as well. It's worth checking the manufacturer's website for documentation, as well as a general internet search for the part number.

In this case, Skyworks' AN619 goes into a lot more detail than their data sheet.

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