lowRISC / opentitan
OpenTitan: Open source silicon root of trust
See what the GitHub community is most excited about today.
OpenTitan: Open source silicon root of trust
Verilator open-source SystemVerilog simulator and lint system
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Common SystemVerilog components
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
VeeR EL2 Core
[UNRELEASED] FP div/sqrt unit for transprecision
RSD: RISC-V Out-of-Order Superscalar Processor
RISC-V Debug Support for our PULP RISC-V Cores
Simple single-port AXI memory interface
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
APB Logic