adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
See what the GitHub community is most excited about this month.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
Verilator open-source SystemVerilog simulator and lint system
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Simple single-port AXI memory interface
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Common SystemVerilog components
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
[UNRELEASED] FP div/sqrt unit for transprecision