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openhwgroup / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

SystemVerilog 484 370 Built by @davidharrishmc @rosethompson @jordancarlin @BBracker @kparry4 5 stars this week
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pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,479 337 Built by @andreaskurth @thommythomaso @micprog @suehtamacv @zarubaf 8 stars this week